Publication detail

Verification of Fault-tolerant methodologies for FPGA Systems

ZACHARIÁŠOVÁ, M. KAŠTIL, J. KOTÁSEK, Z.

Original Title

Verification of Fault-tolerant methodologies for FPGA Systems

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The aim of this paper is to fi nd a way how to utilize and compare diff erent FT methodologies we have been working with during the last few years as well as those which are new in the FT fi eld. Moreover, we present a platform for testing di erent FT methodologies implemented in an FPGA. The testing is based on the software-based injection of an SEU into the selected region of the FPGA from a PC through the JTAG interface. After fault injection into a non-speci c place in the FPGA it is necessary to explore the whole state space using input test vectors.

Keywords

fault-tolerant, FPGA, partial dynamic reconfiguration

Authors

ZACHARIÁŠOVÁ, M.; KAŠTIL, J.; KOTÁSEK, Z.

Released

28. 2. 2012

Publisher

Politecnico di Milano

Location

Annecy

Pages from

55

Pages to

58

Pages count

4

BibTex

@inproceedings{BUT97007,
  author="Marcela {Zachariášová} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Verification of Fault-tolerant methodologies for FPGA Systems",
  booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
  year="2012",
  pages="55--58",
  publisher="Politecnico di Milano",
  address="Annecy"
}