Course detail
Microprocessors
FEKT-BMICAcad. year: 2016/2017
The course is focused on of microprocessor and embedded systems. Students are familiarized with application of microcontrollers, memory systems and memory management. The students will achieve practical experience with programing of the microcontrollers in assembler and C language.
Language of instruction
Czech
Number of ECTS credits
6
Mode of study
Not applicable.
Guarantor
Learning outcomes of the course unit
Graduate should be able to:
- design combination logical circuits,
- design sequence logical circuits based on Moore or Mealy finit state machine,
- design connection of external memory with microcontroller,
- create software for microcontroller in assembly and C language,
- describe memory hierarchy and explain usage of cache memory,
- explain difference between microprocessor, microcontroller, DSP and signal controller,
- explain segmentation, paging and virtual memory.
- design combination logical circuits,
- design sequence logical circuits based on Moore or Mealy finit state machine,
- design connection of external memory with microcontroller,
- create software for microcontroller in assembly and C language,
- describe memory hierarchy and explain usage of cache memory,
- explain difference between microprocessor, microcontroller, DSP and signal controller,
- explain segmentation, paging and virtual memory.
Prerequisites
The student should be able to create simple C language program and explaine function of the elementary electronic parts.
Co-requisites
Not applicable.
Planned learning activities and teaching methods
Techning methods include lectures, computer laboratories. Students have to create six assignments during the course.
Assesment methods and criteria linked to learning outcomes
Up to 40 points for the computer exercises including 10 points for the individual assignments and 30 points for two tests.
Up to 60 points for the final written examination.
Up to 60 points for the final written examination.
Course curriculum
1. Logical function. Boole's algebraic. Simplification of the logical functions. Realization of logical circuits wits NAND and NOR.
2. Binary decoder, multiplexor, demultiplexor, analog multiplexor, priority coder, digital comparator, code transformation.
3. Flip-flop: principle, RS, D, JK, T, master-slave flip-flop. Sequence logical circuits: finite state automat, Huffman's model of sequential automat, Mealy and Moore automat.
4. Data registers, shift registers, synchronous and asynchronous counters, deviders.
5. Von Neumann`s conception of the computer. Base cycle of the computer. Computer block diagram, ALU, controller, registers, memory, peripheral devices. Memory organization. Microprocessor, microcontroller, digital signal processor, digital signal controller.
6. Program, instruction, instruction set, types of instruction. Addressing modes.
7. Machine code, assembler. Subrutins, stacks manipulation. Difference between subrutin and macro.
8. I/O servicing: polling, interrupt-driven I/O, using DMA. Interrupt servicing. Mask, nonmask and pseudomask interrupts. Reset.
9. Peripheral subsystems of microcontrolers: ports, clock generation units, real-time interrupts , watchdog, timers, PWM, A/D and D/A convertors, SCI, SPI, IIC. Freescale HCS08 family microcontrollers.
10. Von Neumann, Harvard and modified Harvard architectures. Pipelining. Superscalar architecture. Multiprocessor systems and processor fields.
11. Memories, memory parameter. Principle and property of memory: SRAM, DRAM, SDRAM, DDR RAM, FeRAM, MRAM, EPROM, EEPROM, FLASH.
12.Memory bus interface. Memory hierarchy, memory cache.
13. Memory management. Address space. Logical and physical address. MMU. Base and limit registers. MMU. Paging and segmentation. Virtual memory.
2. Binary decoder, multiplexor, demultiplexor, analog multiplexor, priority coder, digital comparator, code transformation.
3. Flip-flop: principle, RS, D, JK, T, master-slave flip-flop. Sequence logical circuits: finite state automat, Huffman's model of sequential automat, Mealy and Moore automat.
4. Data registers, shift registers, synchronous and asynchronous counters, deviders.
5. Von Neumann`s conception of the computer. Base cycle of the computer. Computer block diagram, ALU, controller, registers, memory, peripheral devices. Memory organization. Microprocessor, microcontroller, digital signal processor, digital signal controller.
6. Program, instruction, instruction set, types of instruction. Addressing modes.
7. Machine code, assembler. Subrutins, stacks manipulation. Difference between subrutin and macro.
8. I/O servicing: polling, interrupt-driven I/O, using DMA. Interrupt servicing. Mask, nonmask and pseudomask interrupts. Reset.
9. Peripheral subsystems of microcontrolers: ports, clock generation units, real-time interrupts , watchdog, timers, PWM, A/D and D/A convertors, SCI, SPI, IIC. Freescale HCS08 family microcontrollers.
10. Von Neumann, Harvard and modified Harvard architectures. Pipelining. Superscalar architecture. Multiprocessor systems and processor fields.
11. Memories, memory parameter. Principle and property of memory: SRAM, DRAM, SDRAM, DDR RAM, FeRAM, MRAM, EPROM, EEPROM, FLASH.
12.Memory bus interface. Memory hierarchy, memory cache.
13. Memory management. Address space. Logical and physical address. MMU. Base and limit registers. MMU. Paging and segmentation. Virtual memory.
Work placements
Not applicable.
Aims
The aim of the course is to teach the students to design the combination and sequence logical circuits, to give them base information about the principles of the microprocessors systems, the subsystems of the microcontrollers, and the software design for the embedded systems.
Specification of controlled education, way of implementation and compensation for absences
The computer exercises is compulsory, the properly excused missed computer exercises can be compensate.
Recommended optional programme components
Not applicable.
Prerequisites and corequisites
- compulsory prerequisite
Computers and Programming 1
Basic literature
Ličev L., Morkes D., Procesory - architektura, funkce, použití. Brno: Computer press, 1999. 260 s. ISBN 80-7226-172-X. (CS)
Pinker J., Poupa M. Císlicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
Pinker J., Poupa M. Císlicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
Recommended reading
Not applicable.
Classification of course in study plans
Type of course unit
Lecture
26 hod., optionally
Teacher / Lecturer
Syllabus
1. Mathematical logic, logical function, Boole's algebraic. Table, map and algebraical form of logical function. Simplification of logical functions.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
Exercise in computer lab
39 hod., compulsory
Teacher / Lecturer
Syllabus
1. Decimal, hexadecimal and binary numbers. Addition, substraction binary numbers. First complemment. Miltiplication and division binary numbers.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.