Course detail

Logical Systems

FEKT-LLOSAcad. year: 2016/2017

Knowledge of the subject Control Electronics (REB) passed by the student in the batchelor studies is presumpted. This subject gives a broader view on logic systems and their theoretical base (e. g. the morelevel logic and its advantages and disadvantages). A set of themes connected with applications of logic systems in control, in steering of measuring systems, in data acquisition and processing as well as the additional problems like the rise and suppression of disturbance will be discussed. To these themes belong also the design of non-standard logic elements and circuits, the problematics of coding and its use for the safety of data tramission and data storing, the use of the large-scale integration circuits like there are the semiconductor memories, programmable logic arrays and their programming and the auxiliary circuits for microprocessors.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Learning outcomes of the course unit

The student reaches a narrow contact with the digital techniques, with its theoretical base and with the technical means of its practical use.

Prerequisites

The subject knowledge on the Bachelor´s degree level is requested.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods include lecture, numeric laboratories and practical laboratories. Student have to write 7 single projects.

Assesment methods and criteria linked to learning outcomes

Requirements for completion of a course are specified by a regulation issued by the lecturer responsible for the course and updated for every.
up to 30 points for the evaluation and laboratory tests.
up to 70 points for the final written examination.

Course curriculum

1. Boolean algebra.Reduction methods: Karnaugh maps.
2. Reduction methods: Qiune-McCluskey tabular methodAnalysis of logic networks behaviour, signal races, hazards.
3. Adder, multiplexer, demultiplexer, decoder. Asynchronous networks, latches and flip-flops.
4. Sequential logic networks. State machines and their representations.
5. VHDL Language, Data types, VHDL commands
6. Combination a Sequential circuits, State automats. Testing and functional simulation.

Work placements

Not applicable.

Aims

To enlarge the knowledge of logic circuits from the batchelor studies and to fulfil them by the knowledge of the design, construction, testing and practical use.
To give the students the knowledge of syntax and semantics of hardware description language VHDL
VHDL for modelling, simulation and synthesis complex digital syystems.
Programming techniques in XILINX ISE

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Pinker, J. Poupa, M: Číslicové systémy a jazyk VHDL. 2006, ISBN 80-730-0195-5

Recommended reading

Musil, V. a kol.: Navrhování digitálních integrovaných obvodů. Jazyk VHDL [Skriptum FEKT VUT v Brně] Brno 2000 (CS)

Classification of course in study plans

  • Programme EEKR-ML Master's

    branch ML-KAM , 1 year of study, winter semester, compulsory

  • Programme EEKR-ML Master's

    branch ML-KAM , 1 year of study, winter semester, compulsory

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, winter semester, compulsory

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

Syllabus

The continuous and discrete expression of the information by a signal, the terms "the signal quantity" an "the code". The general logic element, its static an dynamic characteristics and its static and dynamic noise immunity. The passive and active logic elemnts. Morelevel and binary logics, the positive and negative logics and the duality of binary logic elements.
The Boolean function and the modes of its inscription (the sentence, the truth-table, the set of status indexes, the Haase´s graph, th Karnagh´s and Svoboda´s chart, the Booleant matrix). The binary and the symmetrical (Gray´s) code. The term "neighbour" and the neighbouring peaks and corps in the Haase´s graph.
The hazards of the first and second order, their elminitation by the aid of the minimization of the Boolean function. The material saves due to this minimization. The minimization of the combinational circuit with one output (the Quine Mc Cluskey´s and Svoboda´s method). The internal and external disturbances.
The minimization of a combinational circuit with more outputs, the evaluation of minimization methods, morelevel combinational circuits.
The general finite automata. Finite automata Mealy and Moore. The term "internal statues" of the finite automata, the evolution table, the transfer table. The Boolean equations and the means of inscription of the time discretization. The asynchronous and synchronous function of the finite automata, the rule of inertia.
The combinational feedback at the final automata and its design. The Boolean equation and its solution by a chart-method. Its one solution and more solutions, the rise of additional for relation between the independent variables.
The ralization of non-standard logic elements. The function of the decision circuit and the logic switch in a logic element.
The transfer of binary signal over a bus, the rise of internal disturbances due to the reflections, the impedances of the inputs and outputs of the logic elements, the transfer capacity an the frequency-band of the bus, binary codes with and without return to zero.
The code methods for the safety of the data transfer on the bus, the detection of one or more errors, the length and cross parity. The cyclic codes, the Bose-Chaudhuri-Hocquent codes, the Reed-Solomon codes and the convolution codes and their encoding and decoding, the Meggit´s decoder.
The semiconductor write/read memories (RAM), their construction from elementary parts, read-only (ROM) memories, programmable ROM, erasable EPROM, electrically erasable EEPROM.
The programmable logic arrays and their architectures, developing systems, the programme PGAL. The testing of a programmed logic array.
The auxiliary and supporting circuits for microprocessors and the circuits of the middle and large scale integration, the basic types and selected single-purpose circuits. VHDL language, basic principles.

Fundamentals seminar

13 hod., compulsory

Teacher / Lecturer

Syllabus

The inscription of the Boolean functions into the charts and graphs, exaples, the minimization of a function with one output only.
The examples of morelevel encoders a the minimization of a group of Boolean functions.
The sequential circuits described as finiote automatas.
The design of the feedback circuits of a finite automata by the aid of the solution of Boolean equations.
The design of a program for programming of a logic array.
The written test

Laboratory exercise

13 hod., compulsory

Teacher / Lecturer

Syllabus

The design of the basic types of the sequential circuits.
The realisation of gigital disign in Spartan Family IC.
The use of VHDL language for design of digital circuits.
The check of the correct function of a programmed logic array and its answers on incorrect input statues.
The check of the correct function of selected circuits of large scale of integration and their insurance against the faults arising due to the incorrect manipulation.