Course detail

Computers and Peripheral Devices

FEKT-MNAVAcad. year: 2017/2018

Basic concepts of computer techniques, architectures, family of x86 microprocessors, addressing modes, cache memory, introduction of multiple units, MMX unit, superscalar architecture of microprocessor, SSE unit, Netburst architecture, multiprocessing and its implementations, microprocessor in the x86-64 mode, architecture of AMD64 microprocessors, DCA, Core and Core iX microarchitectures, AVX unit, Bulldozer and Piledriver microarchitecture, APU and its implementations, system memory, memory timing, synchronous DRAM memories (DDR, DDR2, DDR3), memory modules, buses, hierarchy, internal PC buses, PCI bus, AGP port, PCI-Express bus, HyperTransport and QPI interconnection, DMI, chipset, parameters and properties, chipset evolution, graphics adapter, 2D and 3D acceleration, multiprocessing and its implementation in GPU.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

Ing. Miroslav Balík, Ph.D.

Department

Department of Telecommunications (UTKO)

Learning outcomes of the course unit

Students get a detailed overview of the hardware features of processors, particular computer components of workstations and servers based on the PC platform. Students will be able to program x86 and x86-64 compatible processors on the level of symbolic instructions using standard or vector processing units (MMX, SSE, AVX), and will become familiar with the procedures of parallel programming.

Prerequisites

The subject knowledge on the Bachelor degree level is required.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods depend on the type of course unit as specified in the BUT Rules for Studies and Examinations.
Lectures provide the explanation of basic principles, subject methodology, examples of problems and their solutions.
Computer exercises support practical mastering of themes presented in lectures. Active participation of students is required.
Participation at lectures is recommended. Participation at computer exercises is checked.
Course is taking advantage of e-learning (Moodle) system.

Assesment methods and criteria linked to learning outcomes

Evaluation of study results follows the Rules for Studies and Examinations of BUT and the Dean's Regulation complementing the Rules for Studies and Examinations of BUT. Up to 20 points are given for each of two tests in computer exercises. Up to 60 points are given for the final written examination.

Course curriculum

1. Basic concepts of computer techniques, architectures, bottlenecks,
2. Family of x86, 8086 and 80286 microprocessors, addressing in protected mode,
3. 32-bit x86 microprocessors, 80386, linear addressing using descriptor,
4. Cache memory, 80486, introduction of multiple units, Pentium, MMX unit,
5. Superscalar architecture of microprocessor, Pentium Pro, Pentium II, SSE unit, Pentium III,
6. Netburst architecture, Pentium IV, multiprocessing and its implementations in Pentium IV, GPR registers in x86-64 mode,
7. Architecture of AMD64 microprocessors, DCA, Core and Core iX microarchitectures, AVX unit,
8. Bulldozer and Piledriver microarchitecture, APU and its implementations,
9. System memory, principles, parameters, memory timing, types, asynchronous and synchronous DRAM memories (DDR, DDR2, DDR3), parameters and properties, memory modules,
10. Buses, parameters, types, hierarchy, internal PC buses, PCI bus, AGP port, PCI-Express bus, HyperTransport and QPI interconnection, DMI
11. Chipset, parameters and properties, types, hierarchy, chipset evolution,
12. Graphics adapter, parameters and properties, types, 2D and 3D acceleration, GPU, multiprocessing and its implementation in GPU.

Work placements

Not applicable.

Aims

The aim of the course is to give students detailed information about processor and computer system architecture and programming from the first generation to present processor and computer system generation based on the PC platform, memory subsystem, system buses, chipset, and other particular components of computer system.

Specification of controlled education, way of implementation and compensation for absences

It is obligatory to work through all computer exercises and tests to complete the course. Other forms of checked instruction are specified by a regulation issued by the guarantor of the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Brandejs, M.:Mikroprocesory Intel Pentium a spol.,Grada Publishing, ISBN 80-7169-041-4
Kainka, B. Berndt, H.J.: Využití rozhraní PC pod Windows, HEL, 2000, ISBN 80-86167-13-5
Minasi, M.: PC velký průvodce hardwarem. Grada Publishing, ISBN 80-7169-667-6

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme IBEP-V Master's

    branch V-IBP , 1 year of study, summer semester, elective specialised
    branch V-IBP , 2 year of study, summer semester, elective specialised

  • Programme EEKR-M Master's

    branch M-TIT , 1 year of study, summer semester, elective specialised

  • Programme AUDIO-P Master's

    branch P-AUD , 1 year of study, summer semester, elective specialised

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, summer semester, elective specialised

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Ing. Miroslav Balík, Ph.D.

Syllabus

1. Basic concepts of computer technique, architectures, bottlenecks,
2. Family of x86, 8086 and 80286 microprocessors, addressing in protected mode,
3. 32-bit x86 microprocessors, 80386, linear addressing using descriptor,
4. Cache memory, 80486, introduction of multiple units, Pentium, MMX unit,
5. Superscalar architecture of microprocessor, Pentium Pro, Pentium II, SSE unit, Pentium III,
6. Netburst architecture, Pentium IV, multiprocessing and its implementations in Pentium IV, GPR registers in x86-64 mode,
7. Architecture of AMD64 microprocessors, DCA, Core a Core iX microarchitecture, AVX unit,
8. Bulldozer and Piledriver microarchitecture, APU and its implementations,
9. System memory, principles, parameters, memory timing, types, asynchronous and synchronous DRAM memories (DDR, DDR2, DDR3), parameters and properties, memory modules,
10. Buses, parameters, types, hierarchy, internal PC buses, PCI bus, AGP port, PCI-Express bus, HyperTransport and QPI interconnection, DMI
11. Chipset, parameters and properties, types, hierarchy, chipset evolution,
12. Graphics adapter, parameters and properties, types, 2D a 3D acceleration, GPU, multiprocessing and its implementation on GPU.

Laboratory exercise

39 hod., compulsory

Teacher / Lecturer

Ing. Miroslav Balík, Ph.D.

Syllabus

1. Introduction to assembly language programming, real mode programming environment in x86.
2. Instructions and directives, source code structure in assembly language.
3. Basics of the code structuring, source code compiling, possibilities of the compiling and its utilization.
4. User interface programming in real mode, text and graphic mode, working with macros and subroutines.
5. Asynchronous serial interface programming and its implementation on PC.
6. Computer exercises test no. 1.
7. Win32 API description, introduction to assembly language programming in the Win32 API.
8. Function in assembly language and STDCALL convention, dynamic link library.
9. Math coprocessor x87, MMX programming environment, instruction set and registers.
10. SSE programming environment, instruction set and registers.
11. Multi-threading computing, applications and programming, thread synchronization in Win32 API.
12. Computer exercises test no. 2.