Course detail

Methods of Digital Integrated Circuits Design

FEKT-LNDOAcad. year: 2017/2018

Aspects of design of digital integrated circuits. Used technologies (bipolar, CMOS, BiCMOS. Novel circuit principles, modern digital building block of ASICs. Computer exercices focused on simulation and design of digital functional blocks. Use of professional design system CADENCE for complex design of digital IC (includig layout).

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

doc. Ing. Lukáš Fujcik, Ph.D.

Department

Department of Microelectronics (UMEL)

Learning outcomes of the course unit

Student obtains following knowledge:
- is able to describe required steps in digital integrated circuit design
- is able to design advanced combinational and sequential circuits by usin VHDL
- is able to write basic TCL script for RTL synthesis performed in Cadence RTL Compiler
- is able to do analysis of digital circuit regarding speed, area and power consumption
- is able to use modern design tools for digital integrated circuit design

Prerequisites

Student should know:
- design of advanced combinational and sequential digital circuits by using VHDL
- define proper conditions and specifications according to designed digital circuit
- work with documentation and design any digital circuit according to this specification
- implementation of designed digital system into the programmable circuit
- verification and evaluation of designed digital system

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Techning methods include lectures, computer laboratories and practical laboratories. Course is taking advantage of e-learning (Moodle) system.

Assesment methods and criteria linked to learning outcomes

Requirements for completion of a course are specified by a regulation issued by the lecturer responsible for the course and updated for every.

Course curriculum

1. Complex structures of digital circuits
2. Enhanced VHDL language and advanced syntax
3. Synthesis, static timing analysis, front-end phase
4. Implementation, clock tree synthesis, RC extraction, back-end phase
5. Front-end vs. Back-end
6. Verification - LVS, DRC

Work placements

Not applicable.

Aims

Aim of this course is make students familiar with modern methods for digital IC design. They will be familiar with methods for design of their blocks (including chip layout), with their properties and applications.

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Baker, J.R.:"CMOS circuit design, layout and simulation", IEEE Press a Wiley Interscience, ISBN 0-471-70055-X, 2005

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme EEKR-ML Master's

    branch ML-MEL , 2 year of study, winter semester, elective specialised

  • Programme EEKR-ML Master's

    branch ML-MEL , 2 year of study, winter semester, compulsory

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, winter semester, compulsory

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

Digital integrated ciruits CMOS. Standard familly IC's.
ASICs, programmable devices. IC layout and fabrication.
Basic functional blocks of digital ICs. Combinational logic circuits.
CMOS circuit characterization. Electric-level and logic-level simulation.
Sequential logic circuits. Dynamic logic circuits.
Alternative logic structures (BiCMOS, GaAs).
Sub-system design (adders, parallel multipliers, ROM, RAM, EPROM)
Low-power CMOS logic circuits.
Design methodologies. Design and simulation tools.
Placement and routing, padding. Chip I/O circuits.
Testing, design for testability, design for manufacturability.
VHDL language.
Intellectual property (IP), system on a chip (SOC). Economical aspects of design and production.

Exercise in computer lab

39 hod., compulsory

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

Configuration of design environment, demonstration.
Electrical-level simulation.
Logic simulation, critical path.
Worst-case analysis, hazards.
Basic funtional blocks of digital ICs.
Standard logic famillies of CMOS circuits.
Programmable devices.
Layout and routing.
VHDL - structure and syntax.
VHDL - basic static and dynamic structures.
VHDL - complex example.
Testability, design for test.
Design of ASIC - case study.