Course detail

Logical circuits and systems

FEKT-BPC-LOSAcad. year: 2018/2019

This subject gives a broader view on logic systems and their theoretical base (e. g. the morelevel logic and its advantages and disadvantages). A set of themes connected with applications of logic systems in control, in steering of measuring systems, in data acquisition and processing as well as the additional problems like the rise and suppression of disturbance will be discussed. To these themes belong also the design of non-standard logic elements and circuits, the problematics of coding and its use for the safety of data tramission and data storing, the use of the large-scale integration circuits like there are the semiconductor memories, programmable logic arrays and their programming and the auxiliary circuits for microprocessors.

Language of instruction

Czech

Number of ECTS credits

7

Mode of study

Not applicable.

Learning outcomes of the course unit

The student reaches a narrow contact with the digital techniques, with its theoretical base and with the technical means of its practical use.

Prerequisites

Not applicable.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods include lecture, numeric laboratories and practical laboratories. Student have to write 6 single projects.

Assesment methods and criteria linked to learning outcomes

Requirements for completion of a course are specified by a regulation issued by the lecturer responsible for the course and updated for every.
up to 30 points for the evaluation and laboratory tests.
up to 70 points for the final written examination.

Course curriculum

1. Boolean algebra.
2. Reduction methods: Karnaugh maps.
3. Reduction methods: Qiune-McCluskey tabular method
4.Analysis of logic networks behaviour, signal races, hazards.
5. Adder, multiplexer, demultiplexer, decoder.
6. Asynchronous networks, latches and flip-flops.
7. Sequential logic networks.
8. State machines and their representations.
9. VHDL Language
10. Data types, VHDL commands
11. Combination a Sequential circuits, State automats.
12 Testing and functional simulation.

Work placements

Not applicable.

Aims

To enlarge and to fulfil them by the knowledge of the design, construction, testing and practical use.
To give the students the knowledge of syntax and semantics of hardware description language VHDL
VHDL for modelling, simulation and synthesis complex digital syystems.
Programming techniques in XILINX ISE
NEXYS demoboard.

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

KOLOUCH, J.: Programovatelné logické obvody - Přednášky [Skriptum FEKT VUT v Brně] Brno 2005 (CS)

Recommended reading

PINKER, J.; POUPA, M: Číslicové systémy a jazyk VHDL. 2006, ISBN 80-7300-198-5 (CS)

Classification of course in study plans

  • Programme BPC-AMT Bachelor's 2 year of study, winter semester, compulsory

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Syllabus

The continuous and discrete expression of the information by a signal, the terms "the signal quantity" an "the code". The general logic element, its static an dynamic characteristics and its static and dynamic noise immunity. The passive and active logic elemnts. Morelevel and binary logics, the positive and negative logics and the duality of binary logic elements.
The Boolean function and the modes of its inscription (the sentence, the truth-table, the set of status indexes, the Haase´s graph, th Karnagh´s and Svoboda´s chart, the Booleant matrix). The binary and the symmetrical (Gray´s) code. The term "neighbour" and the neighbouring peaks and corps in the Haase´s graph.
The hazards of the first and second order, their elminitation by the aid of the minimization of the Boolean function. The material saves due to this minimization. The minimization of the combinational circuit with one output (the Quine Mc Cluskey´s and Svoboda´s method). The internal and external disturbances.
The minimization of a combinational circuit with more outputs, the evaluation of minimization methods, morelevel combinational circuits.
The general finite automata. Finite automata Mealy and Moore. The term "internal statues" of the finite automata, the evolution table, the transfer table. The Boolean equations and the means of inscription of the time discretization. The asynchronous and synchronous function of the finite automata, the rule of inertia.
The combinational feedback at the final automata and its design. The Boolean equation and its solution by a chart-method. Its one solution and more solutions, the rise of additional for relation between the independent variables.
The ralization of non-standard logic elements. The function of the decision circuit and the logic switch in a logic element. The contact switches, relays and contactors excited by ac and dc current. The switching of an ohmic, inductive and capacitive load supplied either by dc or ac current.
The rise of the internal disturbances due to the imperfections of the switching elements an their lifetime. The expression of the load by the switch-on an the switch-off power. The cooperation of an electromechanical and a contactless logic element.
The transfer of binary signal over a bus, the rise of internal disturbances due to the reflections, the impedances of the inputs and outputs of the logic elements, the transfer capacity an the frequency-band of the bus, binary codes with and without return to zero.
The code methods for the safety of the data transfer on the bus, the detection of one or more errors, the length and cross parity. The cyclic codes, the Bose-Chaudhuri-Hocquent codes, the Reed-Solomon codes and the convolution codes and their encoding and decoding, the Meggit´s decoder.
The semiconductor write/read memories (RAM), their construction from elementary parts, read-only (ROM) memories, programmable ROM, erasable EPROM, electrically erasable EEPROM.
The programmable logic arrays and their architectures, developing systems, the programme PGAL. The testing of a programmed logic array.
The auxiliary and supporting circuits for microprocessors and the circuits of the middle and large scale integration, the basic types and selected single-purpose circuits.

Laboratory exercise

39 hod., compulsory

Teacher / Lecturer

Syllabus

The measuring of dynamics of the contacless active logic elements, the experimental ascrtaining of their static and dynamic noise immunity.
The measuring of the static characteristic of a dc and ac relay and the measuring of the discontinuity of the switching of its contacts, the prooving of the cooperation of an electromechanical and a contactless switching circuit.
The measuring of the dynamics of an impulse sensor of velocity and the influence of the auxiliary circuits.
The measuring of the basic types of the sequential circuits at different operational modes (the monostable flip-flop prolonging and shortening the input impulse, the influence of the recovery time on the input sensitivity of the circuit).
The check of the correct function of a programmed logic array and its answers on incorrect input statues.
The check of the correct function of selected circuits of large scale of integration and their insurance against the faults arising due to the incorrect manipulation.