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FEKT-BDIOAcad. year: 2018/2019
Fundamentals of digital circuits. VHDL language and general syntax. Concurrent statements, design methodology and examples. Logic hazards, their elimination and avoiding. Sequential statements, design methodology and examples. Metastability. State machine theory and design methodology. Translation of VHDL code to schematic representation (methodology understanding). Practical design of sequential systems and state machines.
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Specification of controlled education, way of implementation and compensation for absences
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Classification of course in study plans
branch B-MET , 2 year of study, summer semester, compulsory
branch EE-FLE , 1 year of study, summer semester, compulsory
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