This course is aimed at teaching advanced techniques of digital circuit design. Firstly, it presents a brief overview of basic approaches to modelling and simulation of digital circuits using the VHDL language and summarizes key properties of target technologies, such as ASIC and FPGA. Next, the course introduces advanced techniques of digital circuits minimization and synthesis (pipelining, retiming), which are supplemented by the application of constraints. The main part of the course is focused on modern approaches to the synthesis of digital circuits. This includes models and methods used for optimisation at logical level and with respect to target technology as well as approaches that build on synergy between synthesis and verification of digital circuits. Apart from these main topics, the course also touches some additional topics like low-power design and the verification of digital circuits based on the OVM methodology.