Course detail

Advanced Digital Systems

FIT-PCSAcad. year: 2019/2020

This course is aimed at teaching advanced techniques of digital circuit design. Firstly, it presents a brief overview of basic approaches to modelling and simulation of digital circuits using the VHDL language and summarizes key properties of target technologies, such as ASIC and FPGA. Next, the course introduces advanced techniques of digital circuits minimization and synthesis (pipelining, retiming), which are supplemented by the application of constraints. The main part of the course is focused on modern approaches to the synthesis of digital circuits. This includes models and methods used for optimisation at logical level and with respect to target technology as well as approaches that build on synergy between synthesis and verification of digital circuits. Apart from these main topics, the course also touches some additional topics like low-power design and the verification of digital circuits based on the OVM methodology.

Language of instruction

Czech

Number of ECTS credits

Mode of study

Not applicable.

Guarantor

doc. Ing. Jan Kořenek, Ph.D.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.

Prerequisites

Digital system design, basic programming skills.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Written mid-term exam and project in due dates.
Exam prerequisites:
Requirements for class accreditation are not defined.

Course curriculum

Not applicable.

Work placements

Not applicable.

Aims

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.

Specification of controlled education, way of implementation and compensation for absences

Presence in any form of instruction is not compulsory. An absence (and hence loss of points) can be compensated in the following ways:

presence in another laboratory group dealing with the same task.
showing a summary of results to the tutor at the next lab.
sending a short report (summarizing the results of the missed lab and answering the questions from the assignment) to the tutor, in 14 days after the missed lab.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

M. Morris Mano, Michael D. Ciletti: Digital Design, ISBN 978-9353062019, 2018 (EN)
Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008 (EN)

Type of course unit

Lecture

26 hod., optionally

Teacher / Lecturer

Ing. Jiří Matoušek, Ph.D.
doc. Ing. Jan Kořenek, Ph.D.
Ing. Lukáš Kekely, Ph.D.
doc. Ing. Tomáš Martínek, Ph.D.

Syllabus

Combinatorial and sequential logic design techniques, algorithms, and tools review.
Review of digital design target technologies (ASIC, FPGA).
Algorithms for minimization of digital circuits.
Advanced synthesis techniques (pipelining, retiming).
Constraint conditions.
Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
Modern synthesis of digital circuits (logic optimization).
Modern synthesis of digital circuits (optimization for target technology).
Synergy between synthesis and verification of digital circuits.
Low power design methodologies.
Reconfigurable computing.
Verification of digital circuits (OVM methodology).

Exercise in computer lab

10 hod., compulsory

Teacher / Lecturer

Ing. Marcela Zachariášová, Ph.D.
Ing. Lukáš Kekely, Ph.D.
Ing. Jiří Matoušek, Ph.D.

Syllabus

Synthesis of the basic logic circuits, pipelining, retiming.
Constraint conditions.
Synthesis of basic digital circuits using ABC tool.
Synthesis of advanced digital circuits using ABC tool.
Verification of digital circuits.

Project

16 hod., compulsory

Teacher / Lecturer

Ing. Marcela Zachariášová, Ph.D.
Ing. Jiří Matoušek, Ph.D.
Ing. Lukáš Kekely, Ph.D.

Syllabus

Individual project focused on synthesis of digital circuits.

VUT

Faculties

University Institutes

Parts

Advanced Digital Systems

Type of course unit