Course detail

Real Time Operating Systems

FEKT-NRTSAcad. year: 2019/2020

This module provides an introduction to the theoretical and practical aspects of implementation control task into the real-time operating system. The module structure enables to meet the students step-by-step with the important features related to design of control system like: Task analysis, choosing suitable hardware architecture and real-time operating system, design simultaneous processes and synchronization with respect to the time boundaries and shared resources, synthesis and verification of the control task on the target platform. Module introduces student with the methodology analyse-verify-implement in order to achieve higher reliability and safety of the entire system. Most of the theoretical findings are explored on practical examples and the good understanding of the module’s content is examined by the final project.

Language of instruction

English

Number of ECTS credits

5

Mode of study

Not applicable.

Learning outcomes of the course unit

By the end of the module, the student will be able to:
Explain basic terms in the area of real-time operating systems, planning and scheduling algorithms, synchronization of the parallel tasks, symmetric and asymmetric multiprocessing.
Define basic performance characteristic of the specific real-time operating system either from documentation or from the suitable performed experiments.
Describe architecture x86 and ARM and to make a qualified decision about utilization of it for a specific task.
Analyse and evaluate for a specific task hardware and software requirement of the control system.
Analyse and evaluate for a specific task its time boundaries.
Analyse and evaluate for a specific task shared resources and to choose and implement suitable algorithm for the resource access and synchronisation.
Generate an analysis, verification and synthesis of the critical parts of a task in a suitable tool.
Identify simultaneous parts of the task and to implement them in the selected API.
Identify and evaluate basic characteristics of the system with respect to the Fault-tolerant behaviour.

Prerequisites

Student should have sufficient competences from practical programming in a higher programming language like C, C++ or C#. Student should be able to analyse a task that is described verbally or by a diagram. Great advantage is a determination to work individually or within a team on the project related to control systems.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

The module will be regularly lectured with laboratory exercises, home works and a final project according to the paragraph 7 of BUT Rules for Studies and Examinations.

Assesment methods and criteria linked to learning outcomes

In accordance with the paragraph 13 BUT Rules for Studies and Examinations, the percentage gain from different activities in this module is as follow:
10 % home works.
70 % final project.
20 % final exam.
Only students with submitted and evaluated final project are allowed to proceed to the final exam.

Course curriculum

1. Old fashioned control systems, advantages and disadvantages.
2. Multitasking operating system. Overview of RTOS.
3. Task synchronization (event, mutex, semafor, critical section, shared object).
4. Deadlines (Race condition, deadlock, livelock, starvation, priority inversion).
5. Scheduling algorithms for uniprocessor and multiprocessor architectures. Architecture x86 and ARM.
6. Basic terms and definitions in RTOS.
7. Analysis of the RTOS parameters, time driven and event driven systems.
8. Analysis of the real-time control task requirements.
9. Analysis, verification and implementation of the task.
10. HMI systems, relation to non-real-time systems.
11. Memory management in RTOS.
12. Fault-tolerant systems.

Work placements

Not applicable.

Aims

In this module students will learn how to implement control algorithms into 32bits real-time operating systems with respect to the reliability and safety of the control system.

Specification of controlled education, way of implementation and compensation for absences

Controlled tuition in this module is determined by the paragraph 7.5 of BUT Rules for Studies and Examinations and it is performed by a lecturer in accordance with the common sense in the academic sphere.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Douglas, B., P. Doing Hard Time, Reading, Mass.:Addison-Wesley, 2000 (EN)

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme EECC-MN Master's

    branch MN-KAM , 1 year of study, winter semester, elective specialised

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Syllabus

1. Introduction into control systems, real-time control systems (RTOS) and technological systems.
2. Loop control, control with operating system and control with RTOS. Multitasking systems. Preemptive and non-preemptive multitasking.
3. Operating system Windows as HMI. Operation principle of Windows. Messages, fronts, events. Process scheduler in Windows. Windows GDI and Windows API. User input/output. File system. WDM, privilege rings.
4. Principle and description of RTOS. Structure and classification of RTOS. Planning algorithms. Core structure of the RTOS, context switching. Process, Thread, Process Synchronization. Semaphores, deadlock, mutex, critical sections. Shared sources exclusive access. Inversion priority. Process monitor.
5. Principle and description of RTOS Windows RTX. Core structure of RTX. RTX and windows. RTX API interface. Basic functions in Windows RTX.
6. Expanded function of Windows RTX.
7. Communication buses and their implementation in RTOS. Industrial buses in control applications. Master/slave architecture. Arbiter, Tokens, Nondeterministic access.
8. Highly Reliable systems. Fault-Tolernat RTOS, Safety-Critical systems. Fail-safe state.
9. Formal methods in design of Fault-Tolerant control systems. Reliability and Reliability indicators. Back-up systems, TMR and NMR systems.
10. Finite Automaton. Timed Automaton. Moore and Mealy implementation in RTOS. Asynchronous and synchronous communication between automaton.
11. Safety programming. Danger SW constructions. WatchDog. Exceptions. Object oriented programming concept and its contribution into Fault-Tolerant.
12. Comparison of RT systems based on PC and PLC. Requirements in technological control. Control system development schedule.

Laboratory exercise

26 hod., optionally

Teacher / Lecturer

Syllabus

1. RTX introduction. Architecture of RTX. RTX API. Configuration RTX Runtime environment. Manual and automatic run of the RTX process. Stopping RTX process.
2. Setting HAL timer. Starvation time settings. Time quantum. Conversion of PCI device from Windows into RTX. Parameters of RTX PCI device. Conversion of PCI device back into Windows. ISA device conversion into RTX and back. Parameters of RTX ISA device.
3. Basic utilities (RTX Properties Control Panel, RTSSrun, RTSSkill, RTSSview, RtxServer). Process and thread in RTX. Memory management. Basic memory functions: RtAllocateLockedMemory a RtFreeLockedMemory.
4. Process management. Functions RtLockProcess a RtUnlockProces. Timer parameters in RTX: RtGetClockTime, RtSetClockTime, RtGetClockResolution a RtGetClockTimerPeriod.
5. Timer functions in RTX: RtCreateTimer, RtDeletTImer, RtCancelTimer, RtSetTimer, RtSetTimerRelative.
6. Shared memory in RTX: RtCreateSharedMemory, RtOpenSharedMemory.
7. Semaphores in RTX: RtCreateSemaphore a RtOpenSemaphore. Events in RTX: RtCreteEvent, RtOpenEvent, RtPulseEvent.
8. RTX and Mutex functions: RtCreateMutex, RtReleaseMutex, RtOpenMutex.
9. RTX and interrupt functions: RtAttachInterruptVector, RtReleaseInterruptVector, RtEnableInterrupts, RtDisableInterrupts.
10. RTX and I/O port functions: RtEnablePortIo, RtDisablePortIo, RtReadPortUchar, RtWritePortUchar.
11. RTX and memoty management functions: RtMapMemory, RtUnamMemory.
12. RTX bus management functions: RtGetBusDataByOffset, RtTransalateBusAddress, RtSetBusDataByOffset. RTX a dll access.