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FIT-IVHAcad. year: 2022/2023
Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
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branch BIT , 2 year of study, summer semester, compulsory-optionalbranch BIT , 1 year of study, summer semester, compulsory-optional
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