Course detail

Computation Systems Architectures

FIT-AVSAcad. year: 2021/2022

The course covers architecture of modern computational systems composed of universal as well as special-purpose processors and their memory subsystems. Instruction-level parallelism is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism are discussed. Data parallelism is illustrated on SIMD streaming instructions and on graphical processors. Programming for shared memory systems in OpenMP follows and then the most proliferated multi-core multiprocessors and the advanced NUMA systems are described. Finally, the generic architecture of the graphics processing units and basic programming techniques using OpenMP are also covered. Techniques of  low-power processors are also explained.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

doc. Ing. Jiří Jaroš, Ph.D.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Overview of the architecture of modern computational systems, their capabilities, limits and future trends. The ability to estimate performance of software applications on a given computer system, identify performance issues and propose their rectification. Practical user experience with supercomputers.
Understanding of hardware limitations having impact on the efficiency of software solutions. 

Prerequisites

Von-Neumann computer architecture, computer memory hierarchy, cache memories and their organization, programming in assembly and in C/C++, compiler's tasks and functions.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Assessment of two projects, 14 hours in total and, computer laboratories and a midterm examination.

Course curriculum

Not applicable.

Work placements

Not applicable.

Aims

To familiarize yourself with the architecture of modern computational systems based on x86, ARM and RISC-V multicore processors in configurations with uniform (UMA) and non-uniform (NUMA) shared memory, often accompanied with a GPU accelerator. To understand hardware aspects of computational systems that have a significant impact on the application performance and power consumption. To be able to assess computing possibilities of a particular architecture and to predict the performance of applications. To clarify the role of a compiler and its cooperation with processors. To be able to orientate oneself on the computational system market, to evaluate and compare various systems.

Specification of controlled education, way of implementation and compensation for absences

  • Missed labs can be substituted in alternative dates.
  • There will be a place for missed labs in the last week of the semester.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Not applicable.

Recommended reading

Agner Fog: Software optimization resources.
Aktuální PPT prezentace přednášek v Elearningu.
Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1. info.
Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 1136 s., ISBN 1-55860-596-7. download.
Materiály ke kurzu Computer Science 152: Computer Architecture and Engineering. http://inst.eecs.berkeley.edu/~cs152/sp13/
van der Pas, R., Stotzer, E., and Terboven, T.: Using OpenMP-The Next Step, MIT Press Ltd, ISBN 9780262534789, 2017. info.

Classification of course in study plans

  • Programme IT-MSC-2 Master's

    branch MBI , 0 year of study, winter semester, elective
    branch MBS , 0 year of study, winter semester, compulsory-optional
    branch MGM , 2 year of study, winter semester, elective
    branch MIN , 0 year of study, winter semester, elective
    branch MIS , 0 year of study, winter semester, elective
    branch MMM , 0 year of study, winter semester, elective
    branch MPV , 2 year of study, winter semester, compulsory
    branch MSK , 2 year of study, winter semester, compulsory-optional

  • Programme MITAI Master's

    specialization NADE , 1 year of study, winter semester, compulsory
    specialization NBIO , 1 year of study, winter semester, compulsory
    specialization NCPS , 1 year of study, winter semester, compulsory
    specialization NEMB , 1 year of study, winter semester, compulsory
    specialization NGRI , 0 year of study, winter semester, compulsory
    specialization NHPC , 1 year of study, winter semester, compulsory
    specialization NIDE , 1 year of study, winter semester, compulsory
    specialization NISD , 0 year of study, winter semester, compulsory
    specialization NMAL , 1 year of study, winter semester, compulsory
    specialization NMAT , 0 year of study, winter semester, compulsory
    specialization NNET , 1 year of study, winter semester, compulsory
    specialization NSEC , 0 year of study, winter semester, compulsory
    specialization NSEN , 1 year of study, winter semester, compulsory
    specialization NSPE , 1 year of study, winter semester, compulsory
    specialization NVER , 0 year of study, winter semester, compulsory
    specialization NVIZ , 1 year of study, winter semester, compulsory
    specialization NISY up to 2020/21 , 0 year of study, winter semester, compulsory
    specialization NISY , 0 year of study, winter semester, compulsory

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Ing. Jiří Jaroš, Ph.D.

Syllabus

  1. Scalar processors, pipelined instruction processing and compiler assistance.
  2. Superscalar processors, dynamic instruction scheduling.
  3. Data flow through the hierarchy of cache memories. 
  4. Branch prediction, optimization of instruction and data fetching.
  5. Processors with data level parallelism.
  6. Multi-threaded and multi-core processors.
  7. Loop parallelism and code vectorization.
  8. Functional parallelism and acceleration of recursive algorithms.
  9. Synchronization on systems with shared memory.
  10. Algorithm for cache coherency.
  11. Architectures with distributed shared memory.
  12. Architecture and programming of graphics processing units.
  13. Low power processors and techniques.

Exercise in computer lab

12 hod., compulsory

Teacher / Lecturer

doc. Ing. Jiří Jaroš, Ph.D.
Ing. Ondřej Olšák
Ing. Michal Piňos
Ing. Vojtěch Mrázek, Ph.D.
Ing. Jakub Chlebík

Syllabus

  1. Performance measurement of sequential code 
  2. Cache blocking, loop swapping and unrolling
  3. OpenMP 4.0 vectorization 
  4. OpenMP loops 
  5. OpenMP tasks
  6. OpenMP sections and mutual exclusion 

Project

14 hod., compulsory

Teacher / Lecturer

Ing. Michal Piňos
Ing. Vojtěch Mrázek, Ph.D.
Ing. Ondřej Olšák
doc. Ing. Jiří Jaroš, Ph.D.
Ing. Jakub Chlebík

Syllabus

  • Performance evaluation and code optimization using OpenMP.
  • Development of an application in OpenMP on a NUMA node.