1. Introduction to the course. Embedded system, hardware and software requirements. Von Neumann architecture, base parts of the computer. Base computer cycle. Harvard architecture, modified Harvard architecture. Memory organization.
2. A program, a machine instruction, instruction sets. Jump instructions. Conditional branch. Conditional instruction execution. Number of the address in the instruction. Addressing modes.
3. A stack. Subroutines, arguments passing, saving a return value. Subroutine vs. macro. C language inline function.
4. Peripheral registers. Memory-mapped, separated and hybrid peripherals. Principles of I/O handling: busy waiting, interrupt, DMA. Interrupts: an interrupt controller, MSI, how CPU service the interrupt. Mask, non-mask and pseudo-mask interrupts. Nested interrupts. Processor RESET.
5. I/O handling software. C language utilization for I/O handling software in embedded systems: volatile keyword, writing of interrupt service routines in C language, peripheral register bit manipulation.
6. Base components of embedded systems: microprocessor, microcontroller, digital signal processor, digital signal controller, System on a Chip (SoC), ASIC. Peripheral subsystems of microcontrollers: ports.
7. Peripheral subsystems of microcontrollers: an interrupt controller, a RESET circuit, a watchdog, a real-time clock, a system clock generating unit, A/D, D/A convertors, counters and timers, Input Capture and Output Compare functions, time interval measurement.
8. Peripheral subsystems of microcontrollers: a PWM subsystem. Serial buses: UART (SCI), SPI, IIC.
9.A semiconductor memory structure. Principle and characteristics of SRAM, DRAM, SDRAM, DDR RAM memories.
10. Principle and characteristics of ROM, EPROM, EEPROM, FLASH (NOR, NAND FLASH), FeRAM, MRAM memories. Embedded system memory subsystem: Serial vs. parallel memory interface. Address decoder. Memory mirroring.
11. A pipelining. Branch hazard and resource conflict. CISC, RISC and Post RISC processors.
12. A memory hierarchy. Cache memories. Memory address to cache block mapping. Multilevel caches. Specialized caches
13. Uniprogramming, multiprogramming, time sharing, process, thread. Realtime systems. Memory management: Address space. Logical and physical address, MMU. Contiguous memory allocation, segmentation, paging. TLB. Swapping. Virtual memory. 

• compulsory prerequisite
  Introduction to Programming

• Programme BPC-AMT Bachelor's 2 year of study, summer semester, compulsory