Přístupnostní navigace
E-application
Search Search Close
Course detail
FIT-IVHAcad. year: 2023/2024
Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Language of instruction
Number of ECTS credits
Mode of study
Guarantor
Department
Entry knowledge
Rules for evaluation and completion of the course
Aims
Study aids
Prerequisites and corequisites
Basic literature
Recommended literature
Elearning
Classification of course in study plans
branch BIT , 2 year of study, summer semester, compulsory-optionalbranch BIT , 1 year of study, summer semester, compulsory-optional
Seminar
Teacher / Lecturer
Syllabus
Project