Course detail

Digital Systems Design

FIT-INCAcad. year: 2024/2025

Binary number system: positional notation, conversion of the base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, the design of combinatorial logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Simple asynchronous networks: design and analysis of behaviour. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronized sequential networks: state coding, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families. Programmable logic devices. 

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

doc. Dr. Ing. Otto Fučík

Department

Department of Computer Systems (UPSY)

Entry knowledge

The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.

Rules for evaluation and completion of the course

Standard students in Czech Programme:
  • Mid-term exam: 25 points.
  • Homework and its evaluation in PC laboratory: 20 points.
  • Final exam: 55 points.
The passing boundary for ECTS assessment: 50 points

International students:
  • Test: 20 points.
  • Mid-term exam: 20 points.
  • Final exam: 60 points.
The passing boundary for ECTS assessment: 50 points.

The knowledge of students is examined by the mid-exam (25 points), the project (20 points), and by the final exam.

The minimal number of points, which can be obtained from the final exam, is 25 (of 55 points). Otherwise, no points will be assigned to a student.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.

Aims

The goal is to obtain fundamental knowledge of methods for description, analysis, and design of combinatorial and sequential logic networks in digital systems.
Fundamental knowledge of selected methods for description, analysis and design of combinatorial and sequential logic in digital systems. 

Study aids

Not applicable.

Prerequisites and corequisites

Basic literature

Harris, D., Harris, S.: Digital Design and Computer Architecture 2nd Edition, Morgan Kaufmann, eBook ISBN: 9780123978165, paperback ISBN: 9780123944245, 2012. (EN)
Mano, M. M. R, Ciletti, D.: Digital Design (4th Edition), Prentice-Hall, ISBN:0131989243, 2006. (EN)
Wakerly, J. F.: Digital Design: Principles and Practices (4th Edition, Book only) 4th Edition, PEARSON, ISBN: 9788131713662, 8131713660, Edition: 4th Edition, 2008. (EN)

Recommended reading

Eysselt, M.: Logická a funkční schémata, výňatek z oborové normy ONT345553. Studijní opora, Učební text, FIT, 2002, 30 str. Tento text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
Eysselt, M.: Vybrané příklady podporující návrh číslicových systémů. Studijní opora, Učební text, FIT, 2002, 38 str. Tento text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
Eysselt. M.: Funkční značky integrovaných obvodů, kreslení spojů. Studijní opora, Učební text, FIT, 2002, 12 str. Tento učební text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
Eysselt, M.: Digital Systems Design: Programmable Logic Devices. Studijní opora, Učební text, FIT VUT v Brně, 2003. Zde je WWW verze přístupná evidovaným studentům.
Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

Wakerly, J. F.: Digital Design: Principles and Practices (4th Edition, Book only) 4th Edition, PEARSON, ISBN: 9788131713662, 8131713660, Edition: 4th Edition, 2008.

Classification of course in study plans

  • Programme BIT Bachelor's 1 year of study, summer semester, compulsory
  • Programme BIT Bachelor's 1 year of study, summer semester, compulsory

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík
doc. Ing. Jan Kořenek, Ph.D.
Ing. Jiří Matoušek, Ph.D.

Syllabus

  1. Binary number system: binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, logic expressions.
  3. Reduction methods: Karnaugh maps, Quine-McCluskey tabular method, Petrick's cover function.
  4. Logic and functional diagrams. Analysis of logic networks behaviour: signal races, hazards.
  5. Combinational logic: multiplexer, demultiplexer, decoder, coder.
  6. Combinational logic: comparator, adder, subtractor, arithmetic and logic unit.
  7. State machines and their representations. Latches and flip-flops.
  8. Synchronized sequential networks: state coding, optimization and implementation.
  9. Sequential logic: Registers, counters, shift registers, frequency dividers.
  10. VHDL language, logic circuits synthesis.
  11. Design of simple digital circuits: CAD tools, design methodology.
  12. Programmable logic devices.
  13. Integrated circuits families.

Seminar

10 hod., compulsory

Teacher / Lecturer

doc. Ing. Jan Kořenek, Ph.D.
Ing. Jiří Matoušek, Ph.D.
Ing. Lukáš Kekely, Ph.D.
doc. Dr. Ing. Otto Fučík

Syllabus

  1. Binary number system: positional notation, conversion of the base, binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
  3. Logic expressions. Quine-McCluskey tabular reduction method, Petrick's cover function.
  4. Reduction methods: Karnaugh maps, logic and functional diagrams.
  5. Logic functions implementation using logic components.
  6. Selected logic modules: multiplexer, demultiplexer, encoder, decoder, adder, ALU.
  7. State machines and their representations. Design of synchronized sequential networks.
  8. Design of logic networks using programmable logic devices.

Project

3 hod., compulsory

Teacher / Lecturer

Ing. Lukáš Kekely, Ph.D.

Syllabus

  1. Three-hour project.