Course detail

Basics on RISC-V Architecture

FEKT-MPA-RSC1Acad. year: 2025/2026

The course material will convey both technical and industry requirements to enable proper engineering architectural decisions as well as implementation.
Topics include:
- What is RISC-V
- Why RISC-V
- Purpose of RISC-V International
- RISC-V’s Instruction Set Architecture (ISA)
- Knowing your Processor’s Performance Objectives
- Evaluating your Core’s Performance
- Taking advantage of the open architecture to improve performance
- Developing the Software-Hardware Interface to increase application performance 2-10x
- Does an open standard result in defragmentation of the architecture
- Course project demonstrating application acceleration through RISC-V customization by 2-5x 

 

Language of instruction

English

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

doc. Ing. Lukáš Fujcik, Ph.D.

Department

Department of Microelectronics (UMEL)

Entry knowledge

Logic Design
Undergraduate Computer Architecture or Computer Organization course
Programming in C (or C++)  

Rules for evaluation and completion of the course

There will be a mid-term and final examination.  
The mid-term and final examination are to be done using individual effort alone.

The course grade will be based on in-class participation, homework assignments, quizzes, course project, and 2 exams. The grade proportions are as follows:
• Homework 15%
• Project 40%
• Mid-Term 20%
• Final Exam: 25% 

 Upon the professor’s discretion, assignment of grades can be based on both absolute and relative standards if it would be helpful to the overall class.  To receive an A grade in this assignment of grades option, a student must show mastery of the material and need to acquire more than 90% of the points possible.  A student earning less than 50% of the points possible will be given a failing grade.  In between these marks, grades will be assigned on a curve using a mean and standard deviation method.

Aims

1. Explain RISC-V to a non-technical person
2. Explain the benefits of RISC-V compared to closed architectures to a technical colleague
3. Know the RISC-V architecture through its assembly language
4. Develop the end processor’s performance objectives by understanding its end application
5. Obtain performance data from your RISC-V processor
6. Through understanding an application’s algorithm and the core’s architecture, develop a software-hardware interface that can be realized through customization to significantly improve performance
7. Enhance a RISC-V processor based on your enhanced software-hardware interface 

 

Study aids

electronic texts, presentations, video tutorials 

 

Prerequisites and corequisites

Not applicable.

Basic literature

Computer Organization and Design RISC-V Edition: The Hardware Software Interface, David A. Patterson (Author), John L. Hennessy (Author), 2023, 736 pages, ISBN 978-0128203316 (EN)
Digital Design and Computer Architecture, RISC-V Edition: RISC-V Edition, Sarah Harris, 2021, 592 pages, ISBN 978-0128200643 (EN)
Volnei A. Pedroni, Circuit Design with VHDL, third edition, 2023, 608 pages, ISBN 978-0262042642 (EN)

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme MPC-NCP Master's 1 year of study, summer semester, compulsory

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

1. What is RISC-V
2. Why RISCV
3. RISCV architecture through its Assembly Language
4. Embedded Processor Architecture Review
5. Application Processor Architecture Review
6. Developing a System Architecture based on an application’s Use Case
7. Defining your performance objectives and your starting point
8. Case Study:  Optimizing Neural Network Classification on a Resource Constrained Processor using Custom Compute
9. How to define a software-hardware interface to maximize performance increase (week 1)
10. Optimizing the algorithm to the software-hardware interface (week 2)
11. Customize the core to implement the newly defined software-hardware interface
12. Does Open Architectures devolve into the defragmentation of the standard?
13. Course Project demos  

 

Exercise in computer lab

26 hod., compulsory

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

Through doing or explaining things to others, you can achieve a much deeper understanding.  Over an eight week project, you will have an opportunity to obtain a deeper understanding of RISC-V architecture through the development of custom instructions to significantly improve the performance of an Artificial Intelligence (AI), Crytpo, or Digital Signal Processing (DSP) application.  It will be a team project of two students per team.  The grading of this project will include a demonstration of your RISC-V core which will include interview grading.