Course detail

Functional Verification of Digital Systems

FIT-FVSAcad. year: 2025/2026

Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping. Validation.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

Ing. Marcela Zachariášová, Ph.D.

Department

Department of Computer Systems (UPSY)

Entry knowledge

Digital system design, basic programming skills.

Rules for evaluation and completion of the course

Labs and project in due dates.

Aims

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.


A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to UVM verification methodology.

Study aids

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

* Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175. * Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217 * Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141. * Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418. 

Recommended reading

Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.
Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
Přednáškové materiály v elektronické formě.
Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.

Classification of course in study plans

  • Programme MITAI Master's

    specialization NSEC , 0 year of study, summer semester, elective
    specialization NISY up to 2020/21 , 0 year of study, summer semester, elective
    specialization NNET , 0 year of study, summer semester, elective
    specialization NMAL , 0 year of study, summer semester, elective
    specialization NCPS , 0 year of study, summer semester, elective
    specialization NHPC , 0 year of study, summer semester, elective
    specialization NVER , 0 year of study, summer semester, elective
    specialization NIDE , 0 year of study, summer semester, elective
    specialization NISY , 0 year of study, summer semester, elective
    specialization NEMB , 0 year of study, summer semester, elective
    specialization NSPE , 0 year of study, summer semester, elective
    specialization NEMB , 0 year of study, summer semester, compulsory
    specialization NBIO , 0 year of study, summer semester, elective
    specialization NSEN , 0 year of study, summer semester, elective
    specialization NVIZ , 0 year of study, summer semester, elective
    specialization NGRI , 0 year of study, summer semester, elective
    specialization NADE , 0 year of study, summer semester, elective
    specialization NISD , 0 year of study, summer semester, elective
    specialization NMAT , 0 year of study, summer semester, elective

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Ing. Marcela Zachariášová, Ph.D.

Syllabus

  1. Motivation and history of verification
  2. Simulation-based verification
  3. Functional verification: introduction
  4. Verification methodologies
  5. Self-checking mechanisms + LAB 1
  6. SystemVerilog: data types, stimuli generation + LAB 2
  7. Coverage analysis + LAB 3
  8. Assertions
  9. Assertions-based verification + LAB 4
  10. Register Abstraction Layer
  11. Invited lecture
  12. Validation
  13. Verification trends

Laboratory exercise

8 hod., optionally

Teacher / Lecturer

Ing. Marcela Zachariášová, Ph.D.

Syllabus

  1. Reference model implementation.
  2. Verification tests implementation.
  3. Coverage-driven verification.
  4. Assertions-based verification.

Project

18 hod., optionally

Teacher / Lecturer

Ing. Marcela Zachariášová, Ph.D.

Syllabus

Design and implementation of verification environment for a selected digital systém.