Course detail

Programmable Logic Devices

FEKT-LPLDAcad. year: 2010/2011

The course is aimed to extend the knowledge of digital technique. Types of programmable devices: SPLD, CPLD and FPGA devices. Special function blocks used in PLD devices. Text description (HDL languages) and graphical description of PLD subsystems. CAD development systems and their use for simulation of digital subsystems (combinational circuits, counters, state machines), synthesis and implementation into CPLD and FPGA devices. Functional verification of designed subsystems by programming laboratory kits.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

Ing. Michal Kubíček, Ph.D.

Department

Department of Radio Electronics (UREL)

Learning outcomes of the course unit

Students acquire survey of the programmable logic device types and of their use in digital design. They become familiar with development systems and with their use for description, synthesis, implementation and simulation of digital systems.

Prerequisites

Knowledge of digital design on the Bachelor´s degree level is requested.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods depend on the type of course unit as specified in the article 7 of BUT Rules for Studies and Examinations.

Assesment methods and criteria linked to learning outcomes

The computer exercises and result of the final examination are evaluated.

Course curriculum

Technology of integrated circuits, ASSP, ASIC, Structured ASIC, PLD.
Architecture of FPGAs, FPGA on the market, future of FPGAs.
Using microcontrollers and other advanced features of FPGAs (gigabit transceivers, MAC, PCI-Express), system on chip (SoC).
VHDL basics, typical coding examples, IP cores and its usage.
Verification: testbench, behavioral simulation, post PAR simulation.
Design of PLD-based systems: power, signal integrity, packing, PCB.

Work placements

Not applicable.

Aims

The aim of the course is extension of knowledge of digital technique, especially of programmable logic devices and FPGAs. Students learn how to use these devices in their digital designs in diploma projects and in practice.

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Not applicable.

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme EEKR-ML Master's

    branch ML-EST , 1 year of study, winter semester, elective specialised

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, winter semester, elective specialised

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Survey of ways how to implement digital systems. Logic functions, their realization in PROM, PAL, PLA structures
Simple PLDs, their functional blocks, macrocells of GAL 16V8 and 20V8 devices. Other SPLD types, their labeling and parameters.
Special PLD types (ZeroPower, low voltage types and others). Programming, programmers
Complex PLD and FPGA devices - structure, basic properties
Implementation of complex combinational functions - multiple-pass and iterative structures, adder, comparator
Asynchronous latches RS and D in PLD structure
Synchronous systems in PLDs: Use of T-type flipflops and EX-OR gates. Mutual conversion of different flipflop types, emulation
One- and bidirectional binary counters, counters with shortened cycle - their description in HDL, number of terms
BCD counters, their implementation in PLD devices
Gray code counters with full and shortened cycle
LFSR counters - structure, advantages and disadvantages, their use
Return of counters into working cycle
State machines (SM): Moore and Mealy type, HDL description, their compilation to SOP form
Simplifying of SM - equivalent states, their finding. State coding for PLDs and FPGAs. Algorithmic description of SM
Timing in programmable devices, pipelining
FPGA devices - additional blocks: I/O standards, memory elements, blocks for frequency synthesis and for further handling of clock signals
Implementation of processors, use of intellectual property blocks
Boundary scan, metastability

Exercise in computer lab

39 hod., compulsory

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Survey of PLD devices and development systems. Basic work with development systems, HDL languages
ABEL language: description of combinational systems - SOP form, compilation, simulation, more complex statements like WHEN-THEN-ELSE, their compilation. Example: priority encoder
Synchronous systems: description methods, examples of various counter types
Fundamentals of VHDL language, behavioral and structural description, concurrent statements and processes. Hierarchically composed designs
Combinational logic description in VHDL, synthesis. Unwanted latch and how to avoid it
Behavioral description of edge-triggered registers. Binary, decade, LFSR counters
State machines: graphical and textual form of state diagram, example: bit sequence detectors. Graphical editors of state diagrams, StateCAD tool
Simulation, synthesis and implementation of the designs (continuously in all exercises)