Course detail

Digital Signal Processors

FEKT-MSPRAcad. year: 2010/2011

Definition of digital signal processor, its differences from the other microprocessors. Generations of digital signal processors and their typical features, trends of development. Basic digital signal processor architectures. Freescale fixed-point digital signal processors. Processor core and the sum of peripherals. Memory mapping. Development tools. Instruction set and the way it is applied. Connection with programming in the C-language. Canonic and non-canonic structures for implementing type IIR and FIR digital filters on digital signal processor. Adaptive LMS algorithm and its implementation. Generation of harmonic signal and harmonic analysis, Goertzel's algorithm, structure of FFT algorithm and its types. Floating-point digital signal processors and their distinguishing features. IEEE-754 Standard, fixed- and floating-point number formats. Real-time processing. VLIW architecture.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

doc. Ing. Petr Sysel, Ph.D.

Department

Department of Telecommunications (UTKO)

Learning outcomes of the course unit

The student will be able to design and adapt algorithms of digital signal processing for implementation on digital signal processor. He will be familiar with basic architectures of digital signal processors, their properties, and their employment in practical applications.

Prerequisites

The subject knowledge on the digital signal processing and the microprocessor technology is requested.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods depend on the type of course unit as specified in the article 7 of BUT Rules for Studies and Examinations.

Assesment methods and criteria linked to learning outcomes

Solution of the given project 15 points
Test 10 points
Check exercises 15 points
Written examination 60 points

Course curriculum

1. Generations of digital signal processors, common properties of digital signal processors, von Neumann's architecture, Harvard architecture, parallel processing.
2. Fixed-point and floating-point representations, representations of negative numbers, properties of fixed-point digital signal processors.
3. Architecture of digital signal processors by Freescale, data arithmetic logic unit, registers, specific instructions.
4. Address generation unit, modulo addressing mode, bit-reverse addrressing mode.
5. Program Controller, instruction pipeline, hardware cycles.
6. Program structure and writing in assembler.
7. Program structure and writing in C language, intrinsic functions, pragma directives, integrated development environment.
8. Quantization effects on digital filters characteristics, limit cycles, optimization of digital filters in digital signal processors.
9. FIR and IIR digital filters implementation in digital signal processors.
10. Generation of harmonic signals and harmonic analysis, Goertzel algorithm, implementation of fast Fourier transform.
11. On-chip peripherials, DMA controller, interrupt controller.
12. External buses, external memory interface.
13. Floating-point digital signal processors. VLIW and VLES architecture.

Work placements

Not applicable.

Aims

The aim of the course is to introduce students to the architecture and basic properties of fixed- and floating-point digital signal processors, to describe the method of assembler programming, and to outline the conection with higher programming languages. Also covered is the implementation of algorithms of linear and adaptive digital filtering.

Specification of controlled education, way of implementation and compensation for absences

Lectures are not duly
Computer exercise are duly
Self-dependent project is duly
Written examamination is duly

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Smékal, Z., Sysel, P. Signálové procesory. 1. vydání. Praha: Sdělovací technika, 2006. 283 s. ISBN 80-86645-08-8 (CS)
SMÉKAL, Z., VÍCH, R.: Signal Processing on Digital Signal Processors (Zpracování signálů se signálovými procesory). Radix spol. s.r.o, Praha 1998. ISBN 80-86031-18-7 (In Czech) (CS)

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme EEKR-M Master's

    branch M-SVE , 1 year of study, winter semester, elective interdisciplinary
    branch M-TIT , 2 year of study, winter semester, elective specialised
    branch M-EST , 2 year of study, winter semester, elective specialised
    branch M-BEI , 2 year of study, winter semester, elective interdisciplinary

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, winter semester, elective specialised

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

doc. Ing. Petr Sysel, Ph.D.

Syllabus

1. Generations of digital signal processors, common properties of digital signal processors, von Neumann's architecture, Harvard architecture, parallel processing.
2. Fixed-point and floating-point representations, representations of negative numbers, properties of fixed-point digital signal processors.
3. Architecture of digital signal processors by Freescale, data arithmetic logic unit, registers, specific instructions.
4. Address generation unit, modulo addressing mode, bit-reverse addrressing mode.
5. Program Controller, instruction pipeline, hardware cycles.
6. Program structure and writing in assembler.
7. Program structure and writing in C language, intrinsic functions, pragma directives, integrated development environment.
8. Quantization effects on digital filters characteristics, limit cycles, optimization of digital filters in digital signal processors.
9. FIR and IIR digital filters implementation in digital signal processors.
10. Generation of harmonic signals and harmonic analysis, Goertzel algorithm, implementation of fast Fourier transform.
11. On-chip peripherials, DMA controller, interrupt controller.
12. External buses, external memory interface.
13. Floating-point digital signal processors. VLIW and VLES architecture.

Laboratory exercise

26 hod., compulsory

Teacher / Lecturer

doc. Ing. Petr Sysel, Ph.D.

Syllabus

1. CodeWarrior Development Studio, basic assembler directives.
2. Fixed-point arithmetic, multiplication, saturation, rounding.
3. Core of 56F8367 digital signal processor, examples of using core registers. Implementation of polynomial functions.
4. Address generation unit, implementation of lookup table functions.
5. Indirect addressing, linear and circular addressing.
6. Hardware cycles DO, implementation of FIR digital filters.
7. Implementation of IIR digital filters.
8. Bitwise reversed addressing, implementation of FFT algorithm.
9. Program control unit, implementation of interrupt services.
10. On-chip peripherals, implementation of serial communications.
11. Timer, counter, examples of usage.
12. Implementation of communication between DSP and A/D and D/A converters.
13. Classification of individual projects.