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Detail publikace
SEKANINA, L. VAŠÍČEK, Z.
Originální název
Approximate Circuit Design by Means of Evolvable Hardware
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.
Klíčová slova
approximate circuit, evolutionary design, multiplier, adder
Autoři
SEKANINA, L.; VAŠÍČEK, Z.
Rok RIV
2013
Vydáno
16. 4. 2013
Nakladatel
IEEE Computer Society
Místo
Singapur
ISBN
978-1-4673-5847-7
Kniha
2013 IEEE International Conference on Evolvable Systems (ICES)
Edice
Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)
Strany od
21
Strany do
28
Strany počet
8
URL
https://www.fit.vut.cz/research/publication/10198/
BibTex
@inproceedings{BUT103438, author="Lukáš {Sekanina} and Zdeněk {Vašíček}", title="Approximate Circuit Design by Means of Evolvable Hardware", booktitle="2013 IEEE International Conference on Evolvable Systems (ICES)", year="2013", series="Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)", pages="21--28", publisher="IEEE Computer Society", address="Singapur", doi="10.1109/ICES.2013.6613278", isbn="978-1-4673-5847-7", url="https://www.fit.vut.cz/research/publication/10198/" }