Detail publikace

A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study

HÁZE, J. VRBA, R. SKOČDOPOLE, M. FUJCIK, L.

Originální název

A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper describes a case study of new 12 bit, low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioral modeling regarding low power consumption. The basic blocks topology design is outlined as well. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of opamp etc. is utilized in the design.

Klíčová slova

Pipelined ADC, switched-capacitor technique, portable application, error correction scheme

Autoři

HÁZE, J.; VRBA, R.; SKOČDOPOLE, M.; FUJCIK, L.

Rok RIV

2004

Vydáno

1. 1. 2004

Nakladatel

Czech Republic

Místo

Brno

ISBN

80-214-2701-9

Kniha

Proceedings of 11th International Conference Electronic Devices and Systems EDS 2004

Číslo edice

1

Strany od

169

Strany do

173

Strany počet

5

BibTex

@inproceedings{BUT11374,
  author="Jiří {Háze} and Radimír {Vrba} and Michal {Skočdopole} and Lukáš {Fujcik}",
  title="A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study",
  booktitle="Proceedings of 11th International Conference Electronic Devices and Systems EDS 2004",
  year="2004",
  number="1",
  pages="5",
  publisher="Czech Republic",
  address="Brno",
  isbn="80-214-2701-9"
}