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MRÁZEK, V. VAŠÍČEK, Z.
Originální název
Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
The aim of the paper is to introduce a new parallel approach to evolutionary optimization of digital circuits described on transistor level. The evolutionary optimization is guided by the fitness function employing a simulator of candidate circuits. A new discrete simulator was introduced to achieve a good trade-off between precision and cost of circuit evaluations. The simulator is based on event-driven simulation. Precise numeric SPICE simulator is regularly called to validate simulation results. To increase the speed of evolution, three parallel approaches were proposed: (i) thread level parallelism, (ii) multiple computing nodes which collectively communicate and distribute the best solution, and (iii) client-server architecture eliminating a limited count of SPICE simulator instances.
Klíčová slova
Evolutionary optimization, transistor-level, parallel systems, digital circuits
Autoři
MRÁZEK, V.; VAŠÍČEK, Z.
Vydáno
4. 7. 2017
Nakladatel
Association for Computing Machinery
Místo
Berlin
ISBN
978-1-4503-4939-0
Kniha
GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference
Strany od
1849
Strany do
1856
Strany počet
8
URL
https://www.fit.vut.cz/research/publication/11377/
BibTex
@inproceedings{BUT144422, author="Vojtěch {Mrázek} and Zdeněk {Vašíček}", title="Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming", booktitle="GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference", year="2017", pages="1849--1856", publisher="Association for Computing Machinery", address="Berlin", doi="10.1145/3067695.3084212", isbn="978-1-4503-4939-0", url="https://www.fit.vut.cz/research/publication/11377/" }