Detail publikace

Relaxed equivalence checking: a new challenge in logic synthesis

VAŠÍČEK, Z.

Originální název

Relaxed equivalence checking: a new challenge in logic synthesis

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The functional equivalence has always been the integral part of virtually every logic synthesis tool. The formal equivalence checking represents a key process that helps logic synthesis tool guarantee that two representations of a circuit design exhibit exactly the same behavior. Among others,equivalence checking is routinely applied to prove that a synthesized digital circuit is logically equivalent to the RTL source code. Although formal equivalence checking has matured greatly during the last two decades and designs with millions of gates can be handled and verified in reasonable time, a new challenge has emerged with the recent advent of approaches addressing the problem of synthesis of approximate circuits.

Klíčová slova

equivalence checking, relaxed equivalence checking, logic circuits, formal techniques, sat solvers, binary decision diagrams

Autoři

VAŠÍČEK, Z.

Vydáno

10. 4. 2017

Nakladatel

IEEE Computer Society

Místo

Dresden

ISBN

978-1-5386-0472-4

Kniha

Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems

Strany od

1

Strany do

6

Strany počet

6

URL

https://www.fit.vut.cz/research/publication/11410/

BibTex

@inproceedings{BUT144425,
  author="Zdeněk {Vašíček}",
  title="Relaxed equivalence checking: a new challenge in logic synthesis",
  booktitle="Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems",
  year="2017",
  pages="1--6",
  publisher="IEEE Computer Society",
  address="Dresden",
  doi="10.1109/DDECS.2017.7968435",
  isbn="978-1-5386-0472-4",
  url="https://www.fit.vut.cz/research/publication/11410/"
}