Detail publikace

Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished

ČEŠKA, M. MATYÁŠ, J. MRÁZEK, V. VAŠÍČEK, Z. SEKANINA, L. VOJNAR, T.

Originální název

Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the approximation error. The method integrates in a unique way formal techniques for approximate equivalence checking into a search-based circuit optimisation algorithm. The key idea of our approach is to employ a novel search strategy that drives the search towards promptly verifiable approximate circuits. The method was implemented within the ABC tool and extensively evaluated on functional approximation of multipliers (with up to 32-bit operands) and adders (with up to 128-bit operands). Within a few hours, we constructed a high-quality Pareto set of 32-bit multipliers providing trade-offs between the circuit error and size. This is for the first time when such complex approximate circuits with formal error guarantees have been derived, which demonstrates an outstanding performance and scalability of our approach compared with existing methods that have either been applied to the approximation of multipliers limited to 8-bit operands or statistical testing has been used only. Our approach thus significantly improves capabilities of the existing methods and paves a way towards an automated design process of provably-correct circuit approximations.

Klíčová slova

approximate computing, logical synthesis, genetic programming, formal methods

Autoři

ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T.

Vydáno

24. 4. 2017

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Irvine, CA

ISBN

978-1-5386-3093-8

Kniha

Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Strany od

416

Strany do

423

Strany počet

8

URL

https://www.fit.vut.cz/research/publication/11420/

BibTex

@inproceedings{BUT144430,
  author="Milan {Češka} and Jiří {Matyáš} and Vojtěch {Mrázek} and Zdeněk {Vašíček} and Lukáš {Sekanina} and Tomáš {Vojnar}",
  title="Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished",
  booktitle="Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)",
  year="2017",
  pages="416--423",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Irvine, CA",
  doi="10.1109/ICCAD.2017.8203807",
  isbn="978-1-5386-3093-8",
  url="https://www.fit.vut.cz/research/publication/11420/"
}

Dokumenty

06A_2.pdf