Detail publikace

Input and Output Generation for the Verification of ALU: a Use Case

ČEKAN, O. PÁNEK, R. KOTÁSEK, Z.

Originální název

Input and Output Generation for the Verification of ALU: a Use Case

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.

Klíčová slova

Stimuli generation, arithmetic logic unit, probabilistic constrained grammar, functional verification

Autoři

ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z.

Vydáno

14. 9. 2018

Nakladatel

IEEE Computer Society

Místo

Kazan

ISBN

978-1-5386-5710-2

Kniha

Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018

Strany od

331

Strany do

336

Strany počet

6

URL

https://www.fit.vut.cz/research/publication/11833/

BibTex

@inproceedings{BUT155097,
  author="Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}",
  title="Input and Output Generation for the Verification of ALU: a Use Case",
  booktitle="Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018",
  year="2018",
  pages="331--336",
  publisher="IEEE Computer Society",
  address="Kazan",
  doi="10.1109/EWDTS.2018.8524641",
  isbn="978-1-5386-5710-2",
  url="https://www.fit.vut.cz/research/publication/11833/"
}

Dokumenty

EWDTS18_Cekan_et_al.pdf