Detail publikace

An FPGA-Based Priority Packet Queues

SMÉKAL, D. NÉMETH, F. DVOŘÁK, J.

Originální název

An FPGA-Based Priority Packet Queues

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.

Klíčová slova

Packet Queues; Quality of Service; Shaping Throughput; Limiter; Tocken Bucket; VHDL; FPGA; Netcope Development Kit

Autoři

SMÉKAL, D.; NÉMETH, F.; DVOŘÁK, J.

Vydáno

29. 10. 2019

Nakladatel

IFAC-PapersOnLine

Místo

High Tatras, Slovakia

ISSN

2405-8963

Periodikum

IFAC-PapersOnLine (ELSEVIER)

Ročník

52

Číslo

27

Stát

Nizozemsko

Strany od

377

Strany do

381

Strany počet

5

URL

https://www.sciencedirect.com/science/article/pii/S2405896319326382

BibTex

@inproceedings{BUT159155,
  author="David {Smékal} and František {Németh} and Jan {Dvořák}",
  title="An FPGA-Based Priority Packet Queues",
  booktitle="16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019",
  year="2019",
  series="52",
  journal="IFAC-PapersOnLine (ELSEVIER)",
  volume="52",
  number="27",
  pages="377--381",
  publisher="IFAC-PapersOnLine",
  address="High Tatras, Slovakia",
  doi="10.1016/j.ifacol.2019.12.689",
  issn="2405-8963",
  url="https://www.sciencedirect.com/science/article/pii/S2405896319326382"
}