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PODIVÍNSKÝ, J. ČEKAN, O. KRČMA, M. BURGET, R. HRUŠKA, T. KOTÁSEK, Z.
Originální název
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
A processor forms the basis of almost most of today's electronic devices. In embedded systems, the emphasis is put not only on high performance but also on the small size and low power consumption. Application-specific instruction set processors present a solution that may be optimized for specific applications by different modifications of their parameters where the trade-offs among the parameters may be represented by a Pareto frontier. In this paper, we propose a novel method of Pareto frontier merging to allow the optimization of a processor for a whole set of applications rather than a single one. We provide an experimental evaluation of the method on a model of a RISC-V processor and we show that the proposed method provides better approximation of the source Pareto frontiers than the state-of-the-art methods.
Klíčová slova
Pareto frontier, processor optimization, ASIP
Autoři
PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z.
Vydáno
25. 2. 2020
Nakladatel
IEEE Circuits and Systems Society
Místo
San José
ISBN
978-1-7281-3427-7
Kniha
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)
Strany od
1
Strany do
4
Strany počet
URL
https://www.fit.vut.cz/research/publication/12081/
BibTex
@inproceedings{BUT162659, author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}", title="Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination", booktitle="2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)", year="2020", pages="1--4", publisher="IEEE Circuits and Systems Society", address="San José", doi="10.1109/LASCAS45839.2020.9068954", isbn="978-1-7281-3427-7", url="https://www.fit.vut.cz/research/publication/12081/" }