Detail publikace

Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology

HOLÍK, L. LENGÁL, O. ROGALEWICZ, A. SEKANINA, L. VAŠÍČEK, Z. VOJNAR, T.

Originální název

Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Most design automation methods developed for approximate computing evaluate candidate solutions by applying a set of input vectors and measuring the error of the output vectors with respect to an exact solution. This approach is not, however, applicable when approximating complex combinational or sequential circuits since the error is not computed precisely enough. This paper surveys various methods of formal verification that could be extended for purposes of determining the error of approximation more precisely and formulates this task through a notion of formal relaxed equivalence checking.

Autoři

HOLÍK, L.; LENGÁL, O.; ROGALEWICZ, A.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T.

Vydáno

20. 1. 2016

Místo

Prague

Strany od

1

Strany do

6

Strany počet

6

URL

http://wapco.inf.uth.gr/index.html

BibTex

@inproceedings{BUT168446,
  author="Lukáš {Holík} and Ondřej {Lengál} and Adam {Rogalewicz} and Lukáš {Sekanina} and Zdeněk {Vašíček} and Tomáš {Vojnar}",
  title="Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology",
  booktitle="2nd Workshop on Approximate Computing (WAPCO 2016)",
  year="2016",
  pages="1--6",
  address="Prague",
  url="http://wapco.inf.uth.gr/index.html"
}