Detail publikace

High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories

ORSÁK, M. BENEŠ, T.

Originální název

High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

We present a modular out-of-order architecture for stateful packet classification. The architecture uses DDR4 SDRAM memory to store rules and their state information to support millions of rules. The memory access pattern generated by network traffic significantly degrades the performance of the DDR4. Our architecture contains a cache and aggregation queues to negate this effect. Additionally, the memory subsystem supports a read cancellation and uses an out- of-order pipeline to maximize the main memory's effectiveness further. The rule set update is implemented as a non-blocking operation and can be interleaved with lookup operations without any performance decrease, leading to the same execution time for rule update and rule lookup. The architecture is optimized for the modern data-center's network traffic and a small on-chip memory footprint, making it suitable as an accelerator for the Open vSwitch. As a result, our novel architecture configured with 1 million exact match rules can process traffic up to 202 Gbit/s (300Mp/s) in average case and 51 Gbit/s (76 Mp/s) in the worst case with the use of a common dual-channel 64 bit DDR4-2666 MHz. It uses fewer FPGA resources (excluding cache memory) than the well-known de facto industry standard Xilinx MIG DDR4 controllers. Our proposed architecture enables commodity FPGA cards commonly equipped with DDR4 to process 100 Gbit/s which results in a significant cost reduction of a 100G SmartNICs.

Klíčová slova

100G, cache, external memory, FPGA, LSU, networking, Open vSwitch, OpenFlow, Out-of-Order, packet classfication, SmartNIC, TSS

Autoři

ORSÁK, M.; BENEŠ, T.

Vydáno

7. 4. 2021

Nakladatel

CESNET National Research and Education Network

Místo

Vídeň

ISBN

978-1-6654-3595-6

Kniha

Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021

Strany od

151

Strany do

156

Strany počet

6

URL

BibTex

@inproceedings{BUT169540,
  author="Michal {Orsák} and Tomáš {Beneš}",
  title="High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories",
  booktitle="Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021",
  year="2021",
  pages="151--156",
  publisher="CESNET National Research and Education Network",
  address="Vídeň",
  doi="10.1109/DDECS52668.2021.9417060",
  isbn="978-1-6654-3595-6",
  url="https://www.fit.vut.cz/research/publication/12457/"
}

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