Detail publikace

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening

PÁNEK, R. LOJDA, J. PODIVÍNSKÝ, J. KOTÁSEK, Z.

Originální název

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

A computing power is important in space applications where a utilization of FPGAs is very useful. However, the FPGAs are susceptible to manifestations of radiation which can cause malfunction. Particularly dangerous are configuration memory faults known as Single Event Upsets (SEUs), which can lead to the entire system failure. Therefore, the fault-tolerant techniques are used to prevent system failures. The main motivation for the use of these techniques is to maintain the correct behavior of the system despite the occurrence of faults. In addition to fault masking, which only delay system failures due to fault accumulation, the utilization of fault mitigation by partial dynamic reconfiguration was used. Everything needed is provided by the reconfiguration controller, which is a necessary additional component of the entire system. It is also very convenient to be able to detect the occurrence of fault in the system. After that, the system does not have to be restored unnecessarily, which saves useless work of the controller. The key part is the evaluation of the resilience to faults of the system using the reconfiguration of damaged parts. In all experiments, an experimental platform was used that emulates an electromechanical system, which consists of a robot control unit on an FPGA and a simulation of their behavior on a PC. Artificial faults have been injected into this controller on the FPGA. Furthermore, reliability estimation data, which was collected from our previously published simulations, was verified on a real system in our current experimentation.

Klíčová slova

Fault Tolerance, Partial Dynamic Reconfiguration Controller, FPGA, Reliability Analysis.

Autoři

PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

Vydáno

1. 9. 2021

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Palermo

ISBN

978-1-6654-2703-6

Kniha

Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021

Strany od

553

Strany do

556

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/12489/

BibTex

@inproceedings{BUT175779,
  author="Richard {Pánek} and Jakub {Lojda} and Jakub {Podivínský} and Zdeněk {Kotásek}",
  title="Reliability Analysis of the FPGA Control System with Reconfiguration Hardening",
  booktitle="Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021",
  year="2021",
  pages="553--556",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Palermo",
  doi="10.1109/DSD53832.2021.00089",
  isbn="978-1-6654-2703-6",
  url="https://www.fit.vut.cz/research/publication/12489/"
}

Dokumenty

DSD2021Panek.pdf