Detail publikace

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

KLHŮFEK, J. MRÁZEK, V.

Originální název

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Generators of arithmetic circuits can automatically deliver various implementations of arithmetic circuits that show different tradeoffs between the key circuit parameters (delay, area, power consumption). However, existing (freely-)available generators are limited if more complex circuits with a hierarchical structure and additional architecture optimization are requested. Furthermore, they support only a few output formats. In order to overcome the above-mentioned limitations, we developed a new generator of arithmetic circuits called ArithsGen. ArithsGen can generate specific architectures of signed and unsigned adders and multipliers using basic building elements such as wires and gates.  Compared to existing generators, the user can, for example, specify the type of adders used in multipliers. The tool supports various outputs formats (Verilog, BLIF, C/C++, or integer netlists). ArithsGen was evaluated in the synthesis and optimization of generic customizable accurate and approximate adders and multipliers. Furthermore, we used the circuits generated by ArithsGen as seeds for a tool developed to automatically create approximate implementations of arithmetic circuits. We show that different initial circuits (generated by ArithsGen) significantly impact the properties of these approximate implementations. The tool is available online at https://github.com/ehw-fit/ariths-gen.

Klíčová slova

arithmetic circuit, generator, verilog, verification, approximate computing

Autoři

KLHŮFEK, J.; MRÁZEK, V.

Vydáno

26. 4. 2022

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Prague

ISBN

978-1-6654-9431-1

Kniha

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)

Strany od

44

Strany do

47

Strany počet

4

URL

https://doi.org/10.1109/DDECS54261.2022.9770152

BibTex

@inproceedings{BUT176991,
  author="Jan {Klhůfek} and Vojtěch {Mrázek}",
  title="ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators",
  booktitle="2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)",
  year="2022",
  pages="44--47",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Prague",
  doi="10.1109/DDECS54261.2022.9770152",
  isbn="978-1-6654-9431-1",
  url="https://doi.org/10.1109/DDECS54261.2022.9770152"
}