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MEGO, R. FRÝZA, T.
Originální název
Instruction mapping techniques for processors with very long instruction word architectures
Typ
článek v časopise ve Web of Science, Jimp
Jazyk
angličtina
Originální abstrakt
This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.
Klíčová slova
digital signal processors, parallel architectures, low-level code, instruction mapping, signal-flow graph
Autoři
MEGO, R.; FRÝZA, T.
Vydáno
12. 12. 2022
Nakladatel
FEI STU Bratislava
Místo
Bratislava
ISSN
1339-309X
Periodikum
Journal of Electrical Engineering
Ročník
73
Číslo
6
Stát
Slovenská republika
Strany od
387
Strany do
395
Strany počet
9
URL
http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf
BibTex
@article{BUT180540, author="Roman {Mego} and Tomáš {Frýza}", title="Instruction mapping techniques for processors with very long instruction word architectures", journal="Journal of Electrical Engineering", year="2022", volume="73", number="6", pages="387--395", doi="10.2478/jee-2022-0053", issn="1339-309X", url="http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf" }