Detail publikace

A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC

HÁZE, J. VRBA, R.

Originální název

A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The article describes a new background calibration technique, which is used in a new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the same purpose. The basic problems coupled to SC, such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities, have been taken into account during a design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account, too.

Klíčová slova

Pipelined ADC, switched-capacitors, background calibration, portable devices

Autoři

HÁZE, J.; VRBA, R.

Rok RIV

2006

Vydáno

13. 3. 2006

Nakladatel

IEEE CAS

Místo

Marrakech, Maroko

ISBN

2-908849-17-8

Kniha

ISCCSP Proceedings 2006

Číslo edice

1

Strany od

82

Strany do

85

Strany počet

4

BibTex

@inproceedings{BUT18555,
  author="Jiří {Háze} and Radimír {Vrba}",
  title="A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC",
  booktitle="ISCCSP Proceedings 2006",
  year="2006",
  number="1",
  pages="4",
  publisher="IEEE CAS",
  address="Marrakech, Maroko",
  isbn="2-908849-17-8"
}