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Detail publikace
HLAVIČKA, J. KOTÁSEK, Z. ZBOŘIL, F.
Originální název
Test Overhead Reduction through RT Level Testability Analysis
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
The paper presents a new method of formal testability analysis made on the RT level in PROLOG environment. This analysis is based on a model which classifies the RT level elements into categories by their function during the testing. The results of the analysis are used for designing a combined test mode in which elements accessible through I-paths are tested with a sequence of parallel test vectors whereas the serial scan method is used only for the remaining elements. This leads to savings both in test application time and in chip area overhead.
Klíčová slova
Design for Testability, RT Level Testability Analysis, RT Level Element Classification, Test Application
Autoři
HLAVIČKA, J.; KOTÁSEK, Z.; ZBOŘIL, F.
Vydáno
1. 1. 1997
Nakladatel
unknown
Místo
Cagliary
Strany od
43
Strany do
47
Strany počet
5
BibTex
@inproceedings{BUT191449, author="Jan {Hlavička} and Zdeněk {Kotásek} and František {Zbořil}", title="Test Overhead Reduction through RT Level Testability Analysis", booktitle="Proceedings of the IEEE ETW 1997", year="1997", pages="43--47", publisher="unknown", address="Cagliary" }