Detail publikace

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

BRADÁČ, Z., VALACH, S.

Originální název

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.

Klíčová slova v angličtině

FPGA, FD64, Xilinx, BERT, RocketIO.

Autoři

BRADÁČ, Z., VALACH, S.

Rok RIV

2006

Vydáno

1. 2. 2006

Nakladatel

VUT Brno

Místo

Brno

ISBN

80-214-3130-

Kniha

Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003

Strany od

433

Strany do

436

Strany počet

4

BibTex

@inproceedings{BUT19450,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  year="2006",
  pages="4",
  publisher="VUT Brno",
  address="Brno",
  isbn="80-214-3130-"
}