Detail publikace

FPGA Implementation of an SDDR Core for Radio Transceiver

BOBULA, M.

Originální název

FPGA Implementation of an SDDR Core for Radio Transceiver

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Today technology and efficiency of the hardware components intended for the digital signal processing offers a great potential to revolutionize the way how radio transceivers are designed. The potential to create the IF sampled software defined digital radio (SDDR) cores for the traditional analog systems, as well as for the modern digital communication transceivers utilizing digital techniques of modulation, algorithms of the adaptation, synchronization, and decoding, completely in the digital domain. This work offers a prototype of such SDDR core for the radio data modem implemented mainly in an FPGA. The design itself was preceded by a complete simulation in MATLAB, Simulink.

Klíčová slova

M-CPFSK, SDR, narrowband radio, dynamic range, FPGA, ADC

Autoři

BOBULA, M.

Rok RIV

2006

Vydáno

27. 4. 2006

Nakladatel

Ing. Zdeněk Novotný CSc., Ondráčkova 105, Brno

Místo

VUT BRNO

ISBN

80-214-3161-X

Kniha

Proceedings of the 12th Conference STUDENT EEICT 2006, Volume 2

Strany od

14

Strany do

16

Strany počet

3

BibTex

@inproceedings{BUT23837,
  author="Marek {Bobula}",
  title="FPGA Implementation of an SDDR Core for Radio Transceiver",
  booktitle="Proceedings of the 12th Conference STUDENT EEICT 2006, Volume 2",
  year="2006",
  pages="3",
  publisher="Ing. Zdeněk Novotný CSc., Ondráčkova 105, Brno",
  address="VUT BRNO",
  isbn="80-214-3161-X"
}