Detail publikace

RT Level Test Optimization for Low Power Consumption

ŠKARVADA, J.

Originální název

RT Level Test Optimization for Low Power Consumption

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

The paper deals with low power consumption test optimization for register transfer level (RTL) circuits. A model of circuit under test (CUT), based on the theory of sets and relations is defined. In the model, the power consumption is seen as a parameter depending on circuit structure and input data used for the test. Optimization method to reduce power consumption during test application, is presented.

Klíčová slova

Register transfer level, power consumption optimization, test vectors reordering, scan cells reordering

Autoři

ŠKARVADA, J.

Rok RIV

2007

Vydáno

26. 10. 2007

Nakladatel

Ing. Zdeněk Novotný, CSc.

Místo

Brno

ISBN

978-80-7355-077-6

Kniha

MEMICS proceedings 2007

Strany od

185

Strany do

192

Strany počet

7

BibTex

@inproceedings{BUT25354,
  author="Jaroslav {Škarvada}",
  title="RT Level Test Optimization for Low Power Consumption",
  booktitle="MEMICS proceedings 2007",
  year="2007",
  pages="185--192",
  publisher="Ing. Zdeněk Novotný, CSc.",
  address="Brno",
  isbn="978-80-7355-077-6"
}