Detail publikace

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

STAREČEK, L. SEKANINA, L. KOTÁSEK, Z.

Originální název

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

Klíčová slova

digital circuit, test vector, reconfiguration

Autoři

STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z.

Rok RIV

2008

Vydáno

17. 4. 2008

Nakladatel

IEEE Computer Society

Místo

Bratislava

ISBN

978-1-4244-2276-0

Kniha

Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

Strany od

255

Strany do

258

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/8603/

BibTex

@inproceedings{BUT27766,
  author="Lukáš {Stareček} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
  title="Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration",
  booktitle="Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  year="2008",
  pages="255--258",
  publisher="IEEE Computer Society",
  address="Bratislava",
  isbn="978-1-4244-2276-0",
  url="https://www.fit.vut.cz/research/publication/8603/"
}

Dokumenty

ps3_03.pdf