Detail publikace

Checkers Design for Communication Protocols Based on FPGAs

STRAKA, M.

Originální název

Checkers Design for Communication Protocols Based on FPGAs

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro and Virtex4 FPGAs were used for the implementation.

Klíčová slova

on-line checker, communication protocol, FPGA, LocalLink, VHDL

Autoři

STRAKA, M.

Rok RIV

2008

Vydáno

24. 4. 2008

Nakladatel

Faculty of Information Technology BUT

Místo

Brno

ISBN

978-80-214-3617-6

Kniha

Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4

Strany od

467

Strany do

473

Strany počet

5

URL

https://www.fit.vut.cz/research/publication/8599/

BibTex

@inproceedings{BUT30481,
  author="Martin {Straka}",
  title="Checkers Design for Communication Protocols Based on FPGAs",
  booktitle="Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4",
  year="2008",
  pages="467--473",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  isbn="978-80-214-3617-6",
  url="https://www.fit.vut.cz/research/publication/8599/"
}

Dokumenty

Straka - eeitc2008.pdf