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ŠKARVADA, J. KOTÁSEK, Z. HERRMAN, T.
Originální název
Power Conscious RTL Test Scheduling
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
In the paper, a methodology of power conscious RTL test scheduling is described. The methodology is based on the fact that circuit under analysis (CUA) is partitioned into testable blocks (TB), the information about the partitioning is the input information for the methodology. TBs are mapped into AMI platform, for each TB the sequences of test vectors are then derived, a professional tool is used for this purpose. The sequences of test vectors are then reordered with the goal to reduce power consumption during test application by reducing switching activities. The power consumption estimation is combined with the implemented platform which allows to gain more precise results. The values of TBs power consumption are then used in RTL test scheduling methodology. The goal is to find test schedule with lowest test application time and lower power consumption than the required maximal value.
Klíčová slova
Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming
Autoři
ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.
Rok RIV
2008
Vydáno
2. 6. 2008
Nakladatel
IEEE Computer Society
Místo
Los Alamitos
ISBN
978-0-7695-3277-6
Kniha
Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools
Strany od
721
Strany do
728
Strany počet
8
URL
https://www.fit.vut.cz/research/publication/8700/
BibTex
@inproceedings{BUT30497, author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}", title="Power Conscious RTL Test Scheduling", booktitle="Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools", year="2008", pages="721--728", publisher="IEEE Computer Society", address="Los Alamitos", isbn="978-0-7695-3277-6", url="https://www.fit.vut.cz/research/publication/8700/" }
Dokumenty
dsd08.pdf