Detail publikace

Hardware Accelerators for Cartesian Genetic Programming

VAŠÍČEK, Z. SEKANINA, L.

Originální název

Hardware Accelerators for Cartesian Genetic Programming

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

Klíčová slova

cartesian genetic programming, field programmable gate array, evolutionary design

Autoři

VAŠÍČEK, Z.; SEKANINA, L.

Rok RIV

2008

Vydáno

30. 3. 2008

Nakladatel

Springer Verlag

Místo

Berlin

ISBN

978-3-540-78670-2

Kniha

Eleventh European Conference on Genetic Programming

Edice

Lecture Notes in Computer Science

Strany od

230

Strany do

241

Strany počet

12

URL

https://www.fit.vut.cz/research/publication/8590/

BibTex

@inproceedings{BUT30754,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerators for Cartesian Genetic Programming",
  booktitle="Eleventh European Conference on Genetic Programming",
  year="2008",
  series="Lecture Notes in Computer Science",
  volume="4971",
  pages="230--241",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-78670-2",
  url="https://www.fit.vut.cz/research/publication/8590/"
}

Dokumenty

49710230.pdf