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MIKUŠEK, P. DVOŘÁK, V.
Originální název
On Lookup Table Cascade-Based Realizations of Arbiters
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.
Klíčová slova
LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits
Autoři
MIKUŠEK, P.; DVOŘÁK, V.
Rok RIV
2008
Vydáno
8. 6. 2008
Nakladatel
IEEE Computer Society
Místo
Parma
ISBN
978-0-7695-3277-6
Kniha
11th EUROMICRO Conference on Digital System Design DSD 2008
Strany od
795
Strany do
802
Strany počet
8
URL
https://www.fit.vut.cz/research/publication/8635/
BibTex
@inproceedings{BUT32056, author="Petr {Mikušek} and Václav {Dvořák}", title="On Lookup Table Cascade-Based Realizations of Arbiters", booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008", year="2008", pages="795--802", publisher="IEEE Computer Society", address="Parma", isbn="978-0-7695-3277-6", url="https://www.fit.vut.cz/research/publication/8635/" }