Detail publikace

Fast Packet Classification Algorithm in Hardware

PUŠ, V.

Originální název

Fast Packet Classification Algorithm in Hardware

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. I propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved.

Klíčová slova

Packet classification, hardware

Autoři

PUŠ, V.

Rok RIV

2008

Vydáno

1. 12. 2008

Místo

Vídeň

ISBN

978-3-200-01612-5

Kniha

Junior Scientist Conference 2008

Strany od

65

Strany do

66

Strany počet

2

BibTex

@inproceedings{BUT33439,
  author="Viktor {Puš}",
  title="Fast Packet Classification Algorithm in Hardware",
  booktitle="Junior Scientist Conference 2008",
  year="2008",
  pages="65--66",
  address="Vídeň",
  isbn="978-3-200-01612-5"
}