Detail publikace

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

GAJDA, Z. SEKANINA, L.

Originální název

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.

Klíčová slova

polymorphic circuit, circuit synthesis, evolutionary design, cartesian genetic programming

Autoři

GAJDA, Z.; SEKANINA, L.

Rok RIV

2009

Vydáno

26. 5. 2009

Nakladatel

IEEE Computational Intelligence Society

Místo

NA

ISBN

978-1-4244-2958-5

Kniha

Proc. of 2009 IEEE Congress on Evolutionary Computation

Strany od

1599

Strany do

1604

Strany počet

6

URL

https://www.fit.vut.cz/research/publication/8949/

BibTex

@inproceedings{BUT33725,
  author="Zbyšek {Gajda} and Lukáš {Sekanina}",
  title="Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming",
  booktitle="Proc. of 2009 IEEE Congress on Evolutionary Computation",
  year="2009",
  pages="1599--1604",
  publisher="IEEE Computational Intelligence Society",
  address="NA",
  isbn="978-1-4244-2958-5",
  url="https://www.fit.vut.cz/research/publication/8949/"
}

Dokumenty

gajda_sekanina_cec09.pdf