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STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.
Originální název
Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
Klíčová slova
FPGA, partial reconfiguration, controller, fault tolerant system, architecture
Autoři
STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.
Rok RIV
2010
Vydáno
3. 10. 2010
Nakladatel
IEEE Computer Society
Místo
Tampere
ISBN
978-1-4244-8971-8
Kniha
NORCHIP 2010
Strany od
1
Strany do
4
Strany počet
BibTex
@inproceedings{BUT34857, author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}", title="Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA", booktitle="NORCHIP 2010", year="2010", pages="1--4", publisher="IEEE Computer Society", address="Tampere", isbn="978-1-4244-8971-8" }