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KLEDROWETZ, V.
Originální název
Pipelined ADC Design Requirements
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
The presented work deals with design and analysis of a pipelined analog-to-digital converter (ADC). There exist error sources such as finite DC gain of opamp, capacitor mismatch, opamp bandwidth, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These error sources are explained and their influences on overall parameters of the pipelined ADC are studied. The pipelined ADC was simulated in MATLAB-Simulink and CADENCE simulation environment.
Klíčová slova
Pipelined ADC, MDAC, opamp
Autoři
Rok RIV
2011
Vydáno
28. 4. 2011
Nakladatel
NOVPRESS s.r.o.
Místo
Brno
ISBN
978-80-214-4273-3
Kniha
Proceedings of the 17th Conference STUDENT EEICT 2011
Edice
vol. 3
Číslo edice
1
Strany od
407
Strany do
411
Strany počet
5
BibTex
@inproceedings{BUT36713, author="Vilém {Kledrowetz}", title="Pipelined ADC Design Requirements", booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011", year="2011", series="vol. 3", number="1", pages="407--411", publisher="NOVPRESS s.r.o.", address="Brno", isbn="978-80-214-4273-3" }