Detail publikace

Instructor Selector Generation from Architecture Description

TRMAČ, M. HUSÁR, A. HRANÁČ, J. HRUŠKA, T. MASAŘÍK, K.

Originální název

Instructor Selector Generation from Architecture Description

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level. The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.

Klíčová slova

compiler, instruction selection, LLVM, ISAC

Autoři

TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K.

Rok RIV

2010

Vydáno

24. 11. 2010

Nakladatel

Masaryk University

Místo

Brno

ISBN

978-80-87342-10-7

Kniha

6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Strany od

167

Strany do

174

Strany počet

8

BibTex

@inproceedings{BUT37045,
  author="Miloslav {Trmač} and Adam {Husár} and Jan {Hranáč} and Tomáš {Hruška} and Karel {Masařík}",
  title="Instructor Selector Generation from Architecture Description",
  booktitle="6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2010",
  pages="167--174",
  publisher="Masaryk University",
  address="Brno",
  isbn="978-80-87342-10-7"
}