Detail publikace

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

VAŠÍČEK, Z. SEKANINA, L.

Originální název

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.  

Klíčová slova

image filter, evolvable hardware, FPGA

Autoři

VAŠÍČEK, Z.; SEKANINA, L.

Rok RIV

2007

Vydáno

19. 4. 2007

ISSN

1751-648X

Periodikum

International Journal of Innovative Computing and Applications

Ročník

1

Číslo

1

Stát

Švýcarská konfederace

Strany od

63

Strany do

73

Strany počet

11

BibTex

@article{BUT45160,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="An Evolvable Hardware System in Xilinx Virtex II Pro FPGA",
  journal="International Journal of Innovative Computing and Applications",
  year="2007",
  volume="1",
  number="1",
  pages="63--73",
  issn="1751-648X"
}