Detail publikace

Basic Block of Pipelined ADC Design Requirements

KLEDROWETZ, V. HÁZE, J.

Originální název

Basic Block of Pipelined ADC Design Requirements

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.

Klíčová slova

Pipelined ADC, MDAC, SC technique, MATLAB model, thermal noise, opamp.

Autoři

KLEDROWETZ, V.; HÁZE, J.

Rok RIV

2011

Vydáno

11. 4. 2011

Nakladatel

VUT v Brně

Místo

Brno

ISSN

1210-2512

Periodikum

Radioengineering

Ročník

2011

Číslo

1

Stát

Česká republika

Strany od

234

Strany do

238

Strany počet

5

BibTex

@article{BUT50694,
  author="Vilém {Kledrowetz} and Jiří {Háze}",
  title="Basic Block of Pipelined ADC Design Requirements",
  journal="Radioengineering",
  year="2011",
  volume="2011",
  number="1",
  pages="234--238",
  issn="1210-2512"
}