Detail publikace

VHDL RT Level Parser/Analyser of a Source Code

ZBOŘIL, F.

Originální název

VHDL RT Level Parser/Analyser of a Source Code

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

During our research activities in the field of testability analysis it was revealed that it is reasonable to perform the algorithms not on the VHDL source file, but rather on "an useable database" which reflects the structure of the circuit under analysis and the diagnostic features of the elements and connections between them. For this purpose an interface between VHDL source text and the software performing the analysis was defined. The paper deals with a special parser/analyser that accepts a subset of the IEEE Standard 1076 Hardware Description Language oriented to description of digital circuits on RT level of modelling. The parser/analyser produces a special database of four mutually depending files that is suitable for testability analysis.

Klíčová slova

VHDL, RT Level, Testability Analysis

Autoři

ZBOŘIL, F.

Rok RIV

2001

Vydáno

1. 1. 2000

Nakladatel

Faculty of Electrical Engineering and Informatics, University of Technology Košice

Místo

Košice

ISBN

80-88922-25-9

Kniha

Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000

Strany od

150

Strany do

155

Strany počet

6

BibTex

@inproceedings{BUT5417,
  author="František {Zbořil}",
  title="VHDL RT Level Parser/Analyser of a Source Code",
  booktitle="Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000",
  year="2000",
  pages="150--155",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Košice",
  isbn="80-88922-25-9"
}